configs/spike_riscv32: new defconfig

Buildroot commit [1] updated riscv-isa-sim (Spike), which now includes
a NS16550 uart emulation. This can be used by RV32 Linux Kernel. This
commit introduce a defconfig for running Linux on Spike RISC-V 32-bit
ISA simulator.

[1] 853b7661bf

Signed-off-by: Julien Olivain <ju.o@free.fr>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>

DEVELOPERS

@@ -1758,6 +1758,7 @@ F:	board/technexion/imx8mpico/
 F:	configs/imx8mmpico_defconfig
 F:	configs/imx8mpico_defconfig
 F:	configs/qemu_riscv64_virt_efi_defconfig
+F:	configs/spike_riscv32_defconfig
 F:	configs/spike_riscv64_defconfig
 F:	package/fluid-soundfont/
 F:	package/fluidsynth/

board/spike/riscv32/patches/linux-headers/linux-headers.hash

@@ -0,0 +1 @@
+../linux/linux.hash

board/spike/riscv32/patches/linux/linux.hash

@@ -0,0 +1,2 @@
+# From https://cdn.kernel.org/pub/linux/kernel/v6.x/sha256sums.asc
+sha256  fce3ee728712ed063aa8c14a8756c8ff8c7a46ba3827f61d2b04a73c7cf5dd9e  linux-6.6.35.tar.xz

board/spike/riscv32/patches/opensbi/opensbi.hash

@@ -0,0 +1,2 @@
+# Locally calculated
+sha256  319b62a4186fbce9b81a0c5f0ec9f003a10c808397a72138bc9745d9b87b1eb1  opensbi-1.4.tar.gz

board/spike/riscv32/readme.txt

@@ -0,0 +1,30 @@
+Linux on Spike RISC-V 32-bit ISA simulator
+==========================================
+
+This configuration provides a minimal working setup to run a Linux
+kernel in the Spike RISC-V ISA simulator.
+
+The Spike ISA simulator can be an interresting alternative to Qemu, in
+some specific cases. For example: simulating new instructions (see [1]),
+simulating riscv-openocd/gdb debug sessions (see [2], [3]), or
+generating an accurate per-instruction log of execution (see
+riscv-isa-sim spike -l option)...
+
+To run Buildroot Linux in Spike, use the commands:
+
+    make spike_riscv32_defconfig
+    make
+    ./board/spike/riscv32/start.sh
+
+The boot is made with the standard RISC-V OpenSBI boot loader. In
+order to keep the simulation simple, the rootfs is passed as an initrd
+ramfs.
+
+[1].
+https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#simulating-a-new-instruction
+
+[2].
+https://github.com/riscv-software-src/riscv-isa-sim/tree/v1.1.0#debugging-with-gdb
+
+[3].
+https://github.com/riscv-collab/riscv-openocd

board/spike/riscv32/start.sh

@@ -0,0 +1,23 @@
+#! /bin/sh
+
+SCRIPT_DIR="$(dirname "$0")"
+BR_BASEDIR="$(readlink -e "${SCRIPT_DIR}/../../..")"
+
+# spike uses dtc at runtime startup, so make sure buildroot host
+# directory is in the PATH
+export PATH="${BR_BASEDIR}/output/host/usr/bin:$PATH"
+
+# Use Buildroot host spike by default, but allow the caller to
+# redefine another spike binary
+: "${SPIKE:=spike}"
+
+# Note 1: Kernel with initrd fail to boot on riscv32 when the system
+# has more than 1GB of RAM. So we set exactly this amount of RAM.
+# Note 2: The default spike ISA is RV64IMAFDC_zicntr_zihpm, so we need
+# to force the RV32 ISA here.
+exec "${SPIKE}" \
+    -m1024 \
+    --initrd "${BR_BASEDIR}"/output/images/rootfs.cpio \
+    --isa="RV32IMAFDC_zicntr_zihpm" \
+    "${@}" \
+    "${BR_BASEDIR}"/output/images/fw_payload.elf

configs/spike_riscv32_defconfig

@@ -0,0 +1,17 @@
+BR2_riscv=y
+BR2_RISCV_32=y
+BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_6_6=y
+BR2_GLOBAL_PATCH_DIR="board/spike/riscv32/patches"
+BR2_DOWNLOAD_FORCE_CHECK_HASHES=y
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.6.35"
+BR2_LINUX_KERNEL_DEFCONFIG="rv32"
+BR2_TARGET_ROOTFS_CPIO=y
+# BR2_TARGET_ROOTFS_TAR is not set
+BR2_TARGET_OPENSBI=y
+BR2_TARGET_OPENSBI_CUSTOM_VERSION=y
+BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.4"
+BR2_TARGET_OPENSBI_PLAT="generic"
+BR2_TARGET_OPENSBI_LINUX_PAYLOAD=y
+BR2_PACKAGE_HOST_RISCV_ISA_SIM=y