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configs/octavo_osd32mp1_brk: new defconfig
This patch adds support to Octavo Systems BRK board. We use the TF-A,
U-Boot and Linux versions from ST, Device Trees from Octavo as well as
a U-Boot patch from Octavo.
Reference:
https://octavosystems.com/octavo_products/osd32mp1-brk/
The device tree blobs come from Octavo System:
https://github.com/octavosystems/OSD32MP1-BRK-device-tree.git
The uboot patches come from Octavo System:
https://github.com/octavosystems/BRK_Developer_Package_patches/tree/master/u-boot-v2020.01-stm32mp
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
This commit is contained in:
Kory Maincent
Thomas Petazzoni
parent
343d7940a4
commit
0380696669
@ -1654,6 +1654,10 @@ N: Koen Martens <gmc@sonologic.nl>
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F: package/capnproto/
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F: package/linuxconsoletools/
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N: Kory Maincent <kory.maincent@bootlin.com>
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F: board/octavo/osd32mp1-brk/
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F: configs/octavo_osd32mp1_brk_defconfig
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N: Kurt Van Dijck <dev.kurt@vandijck-laurijssen.be>
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F: package/bcusdk/
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F: package/libpthsem/
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23
board/octavo/osd32mp1-brk/genimage.cfg
Normal file
23
board/octavo/osd32mp1-brk/genimage.cfg
Normal file
@ -0,0 +1,23 @@
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image sdcard.img {
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hdimage {
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gpt = "true"
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}
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partition fsbl1 {
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image = "tf-a-stm32mp157c-osd32mp1-brk.stm32"
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}
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partition fsbl2 {
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image = "tf-a-stm32mp157c-osd32mp1-brk.stm32"
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}
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partition ssbl {
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image = "u-boot.stm32"
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size = 2M
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}
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partition rootfs {
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image = "rootfs.ext4"
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bootable = "yes"
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}
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}
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1167
board/octavo/osd32mp1-brk/linux-dts/stm32mp157c-osd32mp1-brk.dts
Normal file
1167
board/octavo/osd32mp1-brk/linux-dts/stm32mp157c-osd32mp1-brk.dts
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,4 @@
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label osd32mp1-brk-buildroot
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kernel /boot/zImage
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devicetree /boot/stm32mp157c-osd32mp1-brk.dtb
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append root=/dev/mmcblk0p4 rootwait
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File diff suppressed because it is too large
Load Diff
35
board/octavo/osd32mp1-brk/readme.txt
Normal file
35
board/octavo/osd32mp1-brk/readme.txt
Normal file
@ -0,0 +1,35 @@
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OSD32MP1-BRK
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Intro
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=====
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This configuration supports the OSD32MP1-BRK platform:
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https://octavosystems.com/octavo_products/osd32mp1-brk/
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How to build
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============
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$ make octavo_osd32mp1_brk_defconfig
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$ make
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How to write the microSD card
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=============================
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Once the build process is finished you will have an image called
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"sdcard.img" in the output/images/ directory.
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Copy the bootable "sdcard.img" onto an microSD card with "dd":
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$ sudo dd if=output/images/sdcard.img of=/dev/sdX
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Boot the board
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==============
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(1) Insert the microSD card.
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(2) Plug an USB-SERIAL cable on the RX, TX and GND pins
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(3) Plug a micro-USB cable to power-up the board.
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(4) The system will start, with the console on UART.
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119
board/octavo/osd32mp1-brk/tfa-dts/osd32mp1_ddr.dtsi
Normal file
119
board/octavo/osd32mp1-brk/tfa-dts/osd32mp1_ddr.dtsi
Normal file
@ -0,0 +1,119 @@
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/*
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* Copyright (C) 2015-2018, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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*
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*/
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/*
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* File generated by STMicroelectronics STM32CubeMX DDR Tool for MPUs
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* DDR type: DDR3 / DDR3L
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* DDR width: 16bits
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* DDR density: 4Gb
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* System frequency: 533000Khz
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* Relaxed Timing Mode: false
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* Address mapping type: RBC
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*
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* Save Date: 2020.08.27, save Time: 15:22:11
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*/
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#define DDR_MEM_NAME "DDR3-DDR3L 16bits 533000Khz"
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#define DDR_MEM_SPEED 533000
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#define DDR_MEM_SIZE 0x20000000
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#define DDR_MSTR 0x00041401
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#define DDR_MRCTRL0 0x00000010
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#define DDR_MRCTRL1 0x00000000
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#define DDR_DERATEEN 0x00000000
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#define DDR_DERATEINT 0x00800000
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#define DDR_PWRCTL 0x00000000
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#define DDR_PWRTMG 0x00400010
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#define DDR_HWLPCTL 0x00000000
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#define DDR_RFSHCTL0 0x00210000
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#define DDR_RFSHCTL3 0x00000000
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#define DDR_RFSHTMG 0x0081008B
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#define DDR_CRCPARCTL0 0x00000000
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#define DDR_DRAMTMG0 0x121B2414
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#define DDR_DRAMTMG1 0x000A041C
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#define DDR_DRAMTMG2 0x0608090F
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#define DDR_DRAMTMG3 0x0050400C
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#define DDR_DRAMTMG4 0x08040608
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#define DDR_DRAMTMG5 0x06060403
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#define DDR_DRAMTMG6 0x02020002
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#define DDR_DRAMTMG7 0x00000202
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#define DDR_DRAMTMG8 0x00001005
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#define DDR_DRAMTMG14 0x000000A0
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#define DDR_ZQCTL0 0xC2000040
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#define DDR_DFITMG0 0x02060105
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#define DDR_DFITMG1 0x00000202
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#define DDR_DFILPCFG0 0x07000000
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#define DDR_DFIUPD0 0xC0400003
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#define DDR_DFIUPD1 0x00000000
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#define DDR_DFIUPD2 0x00000000
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#define DDR_DFIPHYMSTR 0x00000000
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#define DDR_ODTCFG 0x06000600
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#define DDR_ODTMAP 0x00000001
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#define DDR_SCHED 0x00000C01
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#define DDR_SCHED1 0x00000000
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#define DDR_PERFHPR1 0x01000001
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#define DDR_PERFLPR1 0x08000200
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#define DDR_PERFWR1 0x08000400
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#define DDR_DBG0 0x00000000
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#define DDR_DBG1 0x00000000
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#define DDR_DBGCMD 0x00000000
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#define DDR_POISONCFG 0x00000000
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#define DDR_PCCFG 0x00000010
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#define DDR_PCFGR_0 0x00010000
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#define DDR_PCFGW_0 0x00000000
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#define DDR_PCFGQOS0_0 0x02100C03
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#define DDR_PCFGQOS1_0 0x00800100
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#define DDR_PCFGWQOS0_0 0x01100C03
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#define DDR_PCFGWQOS1_0 0x01000200
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#define DDR_PCFGR_1 0x00010000
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#define DDR_PCFGW_1 0x00000000
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#define DDR_PCFGQOS0_1 0x02100C03
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#define DDR_PCFGQOS1_1 0x00800040
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#define DDR_PCFGWQOS0_1 0x01100C03
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#define DDR_PCFGWQOS1_1 0x01000200
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#define DDR_ADDRMAP1 0x00070707
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#define DDR_ADDRMAP2 0x00000000
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#define DDR_ADDRMAP3 0x1F000000
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#define DDR_ADDRMAP4 0x00001F1F
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#define DDR_ADDRMAP5 0x06060606
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#define DDR_ADDRMAP6 0x0F060606
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#define DDR_ADDRMAP9 0x00000000
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#define DDR_ADDRMAP10 0x00000000
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#define DDR_ADDRMAP11 0x00000000
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#define DDR_PGCR 0x01442E02
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#define DDR_PTR0 0x0022AA5B
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#define DDR_PTR1 0x04841104
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#define DDR_PTR2 0x042DA068
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#define DDR_ACIOCR 0x10400812
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#define DDR_DXCCR 0x00000C40
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#define DDR_DSGCR 0xF200011F
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#define DDR_DCR 0x0000000B
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#define DDR_DTPR0 0x38D488D0
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#define DDR_DTPR1 0x098B00D8
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#define DDR_DTPR2 0x10023600
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#define DDR_MR0 0x00000840
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#define DDR_MR1 0x00000000
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#define DDR_MR2 0x00000208
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#define DDR_MR3 0x00000000
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#define DDR_ODTCR 0x00010000
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#define DDR_ZQ0CR1 0x00000038
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#define DDR_DX0GCR 0x0000CE81
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#define DDR_DX0DLLCR 0x40000000
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#define DDR_DX0DQTR 0x00112121
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#define DDR_DX0DQSTR 0x3D200000
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#define DDR_DX1GCR 0x0000CE81
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#define DDR_DX1DLLCR 0x40000000
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#define DDR_DX1DQTR 0x11100121
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#define DDR_DX1DQSTR 0x3D200000
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#define DDR_DX2GCR 0x0000CE80
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#define DDR_DX2DLLCR 0x40000000
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#define DDR_DX2DQTR 0xFFFFFFFF
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#define DDR_DX2DQSTR 0x3DB02000
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#define DDR_DX3GCR 0x0000CE80
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#define DDR_DX3DLLCR 0x40000000
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#define DDR_DX3DQTR 0xFFFFFFFF
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#define DDR_DX3DQSTR 0x3DB02000
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581
board/octavo/osd32mp1-brk/tfa-dts/stm32mp157c-osd32mp1-brk.dts
Normal file
581
board/octavo/osd32mp1-brk/tfa-dts/stm32mp157c-osd32mp1-brk.dts
Normal file
@ -0,0 +1,581 @@
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/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
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/*
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* Copyright (C) STMicroelectronics 2020 - All Rights Reserved
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* Author: STM32CubeMX code generation for STMicroelectronics.
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*/
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/* For more information on Device Tree configuration, please refer to
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* https://wiki.st.com/stm32mpu/wiki/Category:Device_tree_configuration
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*/
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/dts-v1/;
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#include <dt-bindings/pinctrl/stm32-pinfunc.h>
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include <dt-bindings/soc/st,stm32-etzpc.h>
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#include <dt-bindings/power/stm32mp1-power.h>
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#include "osd32mp1_ddr.dtsi"
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#include "stm32mp157.dtsi"
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#include "stm32mp15xc.dtsi"
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#include "stm32mp15xxac-pinctrl.dtsi"
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#include "stm32mp15-ddr.dtsi"
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/ {
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model = "Octavo OSD32MP1 BRK board";
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compatible = "st,stm32mp157c-osd32mp1-brk", "st,stm32mp157";
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memory@c0000000{
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device_type = "memory";
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reg = <0xc0000000 0x20000000>;
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};
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vin:vin{
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compatible = "regulator-fixed";
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regulator-name = "vin";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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};
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aliases{
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serial0 = &uart4;
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};
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chosen{
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stdout-path = "serial0:115200n8";
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};
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clocks {
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clk_lse: clk-lse {
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st,drive = < LSEDRV_MEDIUM_HIGH >;
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};
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};
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};
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&clk_hse {
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st,digbypass;
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};
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&pinctrl {
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sdmmc1_pins_mx: sdmmc1_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */
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<STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */
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<STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */
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<STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */
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<STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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uart4_pins_mx: uart4_mx-0 {
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pins1 {
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pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
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bias-disable;
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};
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pins2 {
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pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
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bias-disable;
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drive-push-pull;
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slew-rate = <0>;
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};
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};
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/* USER CODE BEGIN pinctrl */
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/* USER CODE END pinctrl */
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};
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&pinctrl_z {
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i2c4_pins_z_mx: i2c4_mx-0 {
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pins {
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pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */
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<STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */
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bias-disable;
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drive-open-drain;
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slew-rate = <0>;
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};
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};
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/* USER CODE BEGIN pinctrl_z */
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/* USER CODE END pinctrl_z */
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};
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&rcc {
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st,hsi-cal;
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st,csi-cal;
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st,cal-sec = <60>;
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st,clksrc = <
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CLK_MPU_PLL1P
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CLK_AXI_PLL2P
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||||
CLK_MCU_PLL3P
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||||
CLK_PLL12_HSE
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||||
CLK_PLL3_HSE
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||||
CLK_PLL4_HSE
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CLK_RTC_LSE
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||||
CLK_MCO1_DISABLED
|
||||
CLK_MCO2_DISABLED
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||||
>;
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||||
|
||||
st,clkdiv = <
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1 /*MPU*/
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0 /*AXI*/
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0 /*MCU*/
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1 /*APB1*/
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1 /*APB2*/
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1 /*APB3*/
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1 /*APB4*/
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2 /*APB5*/
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23 /*RTC*/
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0 /*MCO1*/
|
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0 /*MCO2*/
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>;
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||||
st,pkcs = <
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CLK_CKPER_HSE
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||||
CLK_FMC_ACLK
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||||
CLK_QSPI_ACLK
|
||||
CLK_ETH_DISABLED
|
||||
CLK_SDMMC12_PLL4P
|
||||
CLK_DSI_DSIPLL
|
||||
CLK_STGEN_HSE
|
||||
CLK_USBPHY_HSE
|
||||
CLK_SPI2S1_PLL3Q
|
||||
CLK_SPI2S23_PLL3Q
|
||||
CLK_SPI45_HSI
|
||||
CLK_SPI6_HSI
|
||||
CLK_I2C46_HSI
|
||||
CLK_SDMMC3_PLL4P
|
||||
CLK_USBO_USBPHY
|
||||
CLK_ADC_CKPER
|
||||
CLK_CEC_LSE
|
||||
CLK_I2C12_HSI
|
||||
CLK_I2C35_HSI
|
||||
CLK_UART1_HSI
|
||||
CLK_UART24_HSI
|
||||
CLK_UART35_HSI
|
||||
CLK_UART6_HSI
|
||||
CLK_UART78_HSI
|
||||
CLK_SPDIF_PLL4P
|
||||
CLK_FDCAN_PLL4R
|
||||
CLK_SAI1_PLL3Q
|
||||
CLK_SAI2_PLL3Q
|
||||
CLK_SAI3_PLL3Q
|
||||
CLK_SAI4_PLL3Q
|
||||
CLK_RNG1_LSI
|
||||
CLK_RNG2_LSI
|
||||
CLK_LPTIM1_PCLK1
|
||||
CLK_LPTIM23_PCLK3
|
||||
CLK_LPTIM45_LSE
|
||||
>;
|
||||
|
||||
/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
|
||||
pll2: st,pll@1 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <1>;
|
||||
cfg = <2 65 1 0 0 PQR(1,1,1)>;
|
||||
frac = <0x1400>;
|
||||
};
|
||||
|
||||
/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
|
||||
pll3: st,pll@2 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <2>;
|
||||
cfg = <1 33 1 16 36 PQR(1,1,1)>;
|
||||
frac = <0x1a04>;
|
||||
};
|
||||
|
||||
/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
|
||||
pll4: st,pll@3 {
|
||||
compatible = "st,stm32mp1-pll";
|
||||
reg = <3>;
|
||||
cfg = <3 98 5 7 7 PQR(1,1,1)>;
|
||||
};
|
||||
};
|
||||
|
||||
&bsec{
|
||||
board_id:board_id@ec{
|
||||
reg = <0xec 0x4>;
|
||||
st,non-secure-otp;
|
||||
};
|
||||
};
|
||||
|
||||
&cryp1{
|
||||
status = "okay";
|
||||
|
||||
/* USER CODE BEGIN cryp1 */
|
||||
/* USER CODE END cryp1 */
|
||||
};
|
||||
|
||||
&etzpc{
|
||||
st,decprot = <
|
||||
DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_SPI6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_I2C6_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_RNG1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_HASH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_CRYP1_ID, DECPROT_NS_RW, DECPROT_UNLOCK)
|
||||
DECPROT(STM32MP1_ETZPC_DDRCTRL_ID, DECPROT_S_RW, DECPROT_LOCK)
|
||||
DECPROT(STM32MP1_ETZPC_DDRPHYC_ID, DECPROT_S_RW, DECPROT_LOCK)
|
||||
DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_LOCK)
|
||||
DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_LOCK)
|
||||
DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_LOCK)
|
||||
>;
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&hash1{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c4{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c4_pins_z_mx>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
i2c-scl-rising-time-ns = <185>;
|
||||
i2c-scl-falling-time-ns = <20>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
pmic:stpmic@33{
|
||||
compatible = "st,stpmic1";
|
||||
reg = <0x33>;
|
||||
interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
|
||||
regulators{
|
||||
compatible = "st,stpmic1-regulators";
|
||||
buck1-supply = <&vin>;
|
||||
buck2-supply = <&vin>;
|
||||
buck3-supply = <&vin>;
|
||||
buck4-supply = <&vin>;
|
||||
ldo1-supply = <&v3v3>;
|
||||
ldo2-supply = <&vin>;
|
||||
ldo3-supply = <&vdd_ddr>;
|
||||
ldo4-supply = <&vin>;
|
||||
ldo5-supply = <&vin>;
|
||||
ldo6-supply = <&v3v3>;
|
||||
vref_ddr-supply = <&vin>;
|
||||
boost-supply = <&vin>;
|
||||
pwr_sw1-supply = <&bst_out>;
|
||||
pwr_sw2-supply = <&bst_out>;
|
||||
|
||||
vddcore:buck1{
|
||||
regulator-name = "vddcore";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
lp-stop{
|
||||
regulator-on-in-suspend;
|
||||
regulator-suspend-microvolt = <1200000>;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_ddr:buck2{
|
||||
regulator-name = "vdd_ddr";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-suspend-microvolt = <1350000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd:buck3{
|
||||
regulator-name = "vdd";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
st,mask-reset;
|
||||
regulator-initial-mode = <0>;
|
||||
regulator-over-current-protection;
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v3v3:buck4{
|
||||
regulator-name = "v3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
regulator-initial-mode = <0>;
|
||||
lp-stop{
|
||||
regulator-suspend-microvolt = <3300000>;
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v1v8_audio:ldo1{
|
||||
regulator-name = "v1v8_audio";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v3v3_hdmi:ldo2{
|
||||
regulator-name = "v3v3_hdmi";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vtt_ddr:ldo3{
|
||||
regulator-name = "vtt_ddr";
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <750000>;
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
lp-stop{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdd_usb:ldo4{
|
||||
regulator-name = "vdd_usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
standby-ddr-sr{
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vdda:ldo5{
|
||||
regulator-name = "vdda";
|
||||
regulator-min-microvolt = <2900000>;
|
||||
regulator-max-microvolt = <2900000>;
|
||||
regulator-boot-on;
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
v1v2_hdmi:ldo6{
|
||||
regulator-name = "v1v2_hdmi";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
standby-ddr-sr{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
vref_ddr:vref_ddr{
|
||||
regulator-name = "vref_ddr";
|
||||
regulator-always-on;
|
||||
regulator-over-current-protection;
|
||||
lp-stop{
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-sr{
|
||||
regulator-on-in-suspend;
|
||||
};
|
||||
standby-ddr-off{
|
||||
regulator-off-in-suspend;
|
||||
};
|
||||
};
|
||||
|
||||
bst_out:boost{
|
||||
regulator-name = "bst_out";
|
||||
};
|
||||
|
||||
vbus_otg:pwr_sw1{
|
||||
regulator-name = "vbus_otg";
|
||||
};
|
||||
|
||||
vbus_sw:pwr_sw2{
|
||||
regulator-name = "vbus_sw";
|
||||
regulator-active-discharge = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
/* USER CODE END i2c4 */
|
||||
};
|
||||
|
||||
&iwdg2{
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
timeout-sec = <32>;
|
||||
};
|
||||
|
||||
&rcc{
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
|
||||
/* USER CODE BEGIN rcc */
|
||||
/* USER CODE END rcc */
|
||||
};
|
||||
|
||||
&rng1{
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&rtc{
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc1{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdmmc1_pins_mx>;
|
||||
status = "okay";
|
||||
disable-wp;
|
||||
st,neg-edge;
|
||||
bus-width = <4>;
|
||||
vmmc-supply = <&v3v3>;
|
||||
};
|
||||
|
||||
&tamp{
|
||||
status = "okay";
|
||||
secure-status = "okay";
|
||||
|
||||
/* USER CODE BEGIN tamp */
|
||||
/* USER CODE END tamp */
|
||||
};
|
||||
|
||||
&uart4{
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins_mx>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg_hs{
|
||||
status = "okay";
|
||||
phys = <&usbphyc_port1 0>;
|
||||
phy-names = "usb2-phy";
|
||||
usb-role-switch;
|
||||
};
|
||||
|
||||
&usbphyc{
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphyc_port0{
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&usbphyc_port1{
|
||||
phy-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&cpu0{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&cpu1{
|
||||
cpu-supply = <&vddcore>;
|
||||
};
|
||||
|
||||
&pwr_regulators {
|
||||
system_suspend_supported_soc_modes = <
|
||||
STM32_PM_CSLEEP_RUN
|
||||
STM32_PM_CSTOP_ALLOW_LP_STOP
|
||||
STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR
|
||||
>;
|
||||
system_off_soc_mode = <STM32_PM_CSTOP_ALLOW_STANDBY_DDR_OFF>;
|
||||
vdd-supply = <&vdd>;
|
||||
vdd_3v3_usbfs-supply = <&vdd_usb>;
|
||||
};
|
||||
|
||||
&nvmem_layout{
|
||||
nvmem-cells = <&cfg0_otp>,
|
||||
<&part_number_otp>,
|
||||
<&monotonic_otp>,
|
||||
<&nand_otp>,
|
||||
<&uid_otp>,
|
||||
<&package_otp>,
|
||||
<&hw2_otp>,
|
||||
<&pkh_otp>,
|
||||
<&board_id>;
|
||||
|
||||
nvmem-cell-names = "cfg0_otp",
|
||||
"part_number_otp",
|
||||
"monotonic_otp",
|
||||
"nand_otp",
|
||||
"uid_otp",
|
||||
"package_otp",
|
||||
"hw2_otp",
|
||||
"pkh_otp",
|
||||
"board_id";
|
||||
};
|
||||
|
||||
&timers15{
|
||||
secure-status = "okay";
|
||||
st,hsi-cal-input = <7>;
|
||||
st,csi-cal-input = <8>;
|
||||
};
|
||||
60
configs/octavo_osd32mp1_brk_defconfig
Normal file
60
configs/octavo_osd32mp1_brk_defconfig
Normal file
@ -0,0 +1,60 @@
|
||||
# architecture
|
||||
BR2_arm=y
|
||||
BR2_cortex_a7=y
|
||||
|
||||
# global patch directory
|
||||
BR2_GLOBAL_PATCH_DIR="board/octavo/osd32mp1-brk/patches"
|
||||
|
||||
# Linux headers same as kernel, a 5.4 series
|
||||
BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_5_4=y
|
||||
|
||||
# rootfs overlay
|
||||
BR2_ROOTFS_OVERLAY="board/octavo/osd32mp1-brk/overlay/"
|
||||
|
||||
# image generation
|
||||
BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh"
|
||||
BR2_ROOTFS_POST_SCRIPT_ARGS="-c board/octavo/osd32mp1-brk/genimage.cfg"
|
||||
|
||||
# Kernel, use CUSTOM_DTS_PATH associated with INTREE_DTS_NAME to build the right
|
||||
# device-tree
|
||||
BR2_LINUX_KERNEL=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_GIT=y
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/linux.git"
|
||||
BR2_LINUX_KERNEL_CUSTOM_REPO_VERSION="v5.4-stm32mp-r1.1"
|
||||
BR2_LINUX_KERNEL_DEFCONFIG="multi_v7"
|
||||
BR2_LINUX_KERNEL_CONFIG_FRAGMENT_FILES="$(LINUX_DIR)/arch/arm/configs/fragment-01-multiv7_cleanup.config $(LINUX_DIR)/arch/arm/configs/fragment-02-multiv7_addons.config"
|
||||
BR2_LINUX_KERNEL_DTS_SUPPORT=y
|
||||
BR2_LINUX_KERNEL_INTREE_DTS_NAME="stm32mp157c-osd32mp1-brk"
|
||||
BR2_LINUX_KERNEL_CUSTOM_DTS_PATH="board/octavo/osd32mp1-brk/linux-dts/*"
|
||||
BR2_LINUX_KERNEL_INSTALL_TARGET=y
|
||||
BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
|
||||
|
||||
# Filesystem
|
||||
BR2_TARGET_ROOTFS_EXT2=y
|
||||
BR2_TARGET_ROOTFS_EXT2_4=y
|
||||
# BR2_TARGET_ROOTFS_TAR is not set
|
||||
|
||||
# TF-A
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE=y
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_GIT=y
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/arm-trusted-firmware.git"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_REPO_VERSION="v2.2-stm32mp-r2.2"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_PLATFORM="stm32mp1"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_CUSTOM_DTS_PATH="board/octavo/osd32mp1-brk/tfa-dts/*"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_ADDITIONAL_VARIABLES="STM32MP_SDMMC=1 AARCH32_SP=sp_min DTB_FILE_NAME=stm32mp157c-osd32mp1-brk.dtb STM32MP_USB_PROGRAMMER=1"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_IMAGES="*.stm32"
|
||||
BR2_TARGET_ARM_TRUSTED_FIRMWARE_NEEDS_DTC=y
|
||||
|
||||
# U-Boot
|
||||
BR2_TARGET_UBOOT=y
|
||||
BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_GIT=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/STMicroelectronics/u-boot.git"
|
||||
BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="v2020.01-stm32mp-r1.1"
|
||||
BR2_TARGET_UBOOT_BOARD_DEFCONFIG="osd32mp1_brk_trusted"
|
||||
# BR2_TARGET_UBOOT_FORMAT_BIN is not set
|
||||
BR2_TARGET_UBOOT_FORMAT_STM32=y
|
||||
BR2_TARGET_UBOOT_CUSTOM_MAKEOPTS="DEVICE_TREE=stm32mp157c-osd32mp1-brk"
|
||||
|
||||
# Package needed to generate the image
|
||||
BR2_PACKAGE_HOST_GENIMAGE=y
|
||||
Loading…
Reference in New Issue
Block a user