Alan Modra a6743a5420 opcodes error messages ... Another patch aimed at making binutils comply with the GNU coding standard. The generated files require https://sourceware.org/ml/cgen/2018-q1/msg00004.html cpu/ * frv.opc: Include opintl.h. (add_next_to_vliw): Use opcodes_error_handler to print error. Standardize error message. (fr500_check_insn_major_constraints, frv_vliw_add_insn): Likewise. opcodes/ * sysdep.h (opcodes_error_handler): Define. (_bfd_error_handler): Declare. * Makefile.am: Remove stray #. * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT EDIT" comment. * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c, * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c, * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use opcodes_error_handler to print errors. Standardize error messages. * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise, and include opintl.h. * nds32-asm.c: Likewise, and include sysdep.h and opintl.h. * i386-gen.c: Standardize error messages. * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate. * Makefile.in: Regenerate. * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c, * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c, * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c, * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c, * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c, * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c, * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c, * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c, * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c, * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c, * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.		2018-03-03 11:34:26 +10:30
..
ChangeLog	opcodes error messages	2018-03-03 11:34:26 +10:30
cris.cpu
epiphany.cpu	2012-11-30 Oleg Raikhman <oleg@adapteva.com>	2012-11-30 17:54:58 +00:00
epiphany.opc	epiphany/disassembler: Improve alignment of output.	2016-02-02 11:09:17 +00:00
fr30.cpu	Correct fr30 comment	2016-03-03 12:55:30 +10:30
fr30.opc
frv.cpu
frv.opc	opcodes error messages	2018-03-03 11:34:26 +10:30
ip2k.cpu
ip2k.opc
iq10.cpu
iq2000.cpu
iq2000.opc
iq2000m.cpu
lm32.cpu	PR binutils/15241	2013-03-08 17:25:12 +00:00
lm32.opc
m32c.cpu
m32c.opc
m32r.cpu
m32r.opc
mep-avc2.cpu
mep-avc.cpu
mep-c5.cpu
mep-core.cpu
mep-default.cpu
mep-ext-cop.cpu
mep-fmax.cpu
mep-h1.cpu
mep-ivc2.cpu
mep-rhcop.cpu
mep-sample-ucidsp.cpu
mep.cpu
mep.opc	Add fall through comment to source in cpu/	2016-10-06 22:48:37 +10:30
mt.cpu
mt.opc	cpu/	2012-02-27 06:57:57 +00:00
or1k.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
or1k.opc	Whitespace fixes for cpu/or1k.opc	2014-06-12 12:30:57 +09:30
or1kcommon.cpu	Update the openrisc previous program counter (ppc) when running code in the cgen based simulator.	2017-03-20 15:33:51 +00:00
or1korbis.cpu	or1k: add missing l.msync, l.psync and l.psync instructions.	2014-07-20 20:26:09 +03:00
or1korfpx.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
sh64-compact.cpu
sh64-media.cpu
sh.cpu
sh.opc
simplify.inc
xc16x.cpu
xc16x.opc
xstormy16.cpu
xstormy16.opc