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f8a87c78e6
This is *cst = (data[0] << 24) + (data[1] << 16) + (data[2] << 8) + data[3]; data is unsigned char which promotes to int. * h8300-dis.c (extract_immediate): Avoid signed overflow. (bfd_h8_disassemble): Likewise.
725 lines
17 KiB
C
725 lines
17 KiB
C
/* Disassemble h8300 instructions.
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Copyright (C) 1993-2019 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#define DEFINE_TABLE
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#include "sysdep.h"
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#define h8_opcodes h8ops
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#include "opcode/h8300.h"
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#include "disassemble.h"
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#include "opintl.h"
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#include "libiberty.h"
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struct h8_instruction
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{
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int length;
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const struct h8_opcode *opcode;
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};
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struct h8_instruction *h8_instructions;
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/* Run through the opcodes and sort them into order to make them easy
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to disassemble. */
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static void
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bfd_h8_disassemble_init (void)
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{
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unsigned int i;
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unsigned int nopcodes;
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const struct h8_opcode *p;
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struct h8_instruction *pi;
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nopcodes = sizeof (h8_opcodes) / sizeof (struct h8_opcode);
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h8_instructions = xmalloc (nopcodes * sizeof (struct h8_instruction));
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for (p = h8_opcodes, pi = h8_instructions; p->name; p++, pi++)
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{
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/* Just make sure there are an even number of nibbles in it, and
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that the count is the same as the length. */
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for (i = 0; p->data.nib[i] != (op_type) E; i++)
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;
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if (i & 1)
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{
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/* xgettext:c-format */
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opcodes_error_handler (_("internal error, h8_disassemble_init"));
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abort ();
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}
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pi->length = i / 2;
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pi->opcode = p;
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}
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/* Add entry for the NULL vector terminator. */
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pi->length = 0;
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pi->opcode = p;
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}
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static void
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extract_immediate (FILE *stream,
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op_type looking_for,
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int thisnib,
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unsigned char *data,
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int *cst,
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int *len,
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const struct h8_opcode *q)
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{
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switch (looking_for & SIZE)
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{
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case L_2:
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*len = 2;
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*cst = thisnib & 3;
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/* DISP2 special treatment. */
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if ((looking_for & MODE) == DISP)
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{
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if (OP_KIND (q->how) == O_MOVAB
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|| OP_KIND (q->how) == O_MOVAW
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|| OP_KIND (q->how) == O_MOVAL)
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{
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/* Handling for mova insn. */
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switch (q->args.nib[0] & MODE)
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{
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case INDEXB:
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default:
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break;
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case INDEXW:
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*cst *= 2;
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break;
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case INDEXL:
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*cst *= 4;
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break;
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}
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}
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else
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{
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/* Handling for non-mova insn. */
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switch (OP_SIZE (q->how))
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{
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default: break;
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case SW:
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*cst *= 2;
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break;
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case SL:
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*cst *= 4;
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break;
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}
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}
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}
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break;
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case L_8:
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*len = 8;
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*cst = data[0];
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break;
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case L_16:
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case L_16U:
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*len = 16;
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*cst = (data[0] << 8) + data [1];
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#if 0
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if ((looking_for & SIZE) == L_16)
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*cst = (short) *cst; /* Sign extend. */
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#endif
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break;
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case L_32:
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*len = 32;
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*cst = (((unsigned) data[0] << 24) + (data[1] << 16)
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+ (data[2] << 8) + data[3]);
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break;
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default:
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*len = 0;
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*cst = 0;
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fprintf (stream, "DISP bad size\n");
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break;
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}
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}
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static const char *regnames[] =
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{
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"r0h", "r1h", "r2h", "r3h", "r4h", "r5h", "r6h", "r7h",
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"r0l", "r1l", "r2l", "r3l", "r4l", "r5l", "r6l", "r7l"
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};
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static const char *wregnames[] =
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{
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7"
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};
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static const char *lregnames[] =
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{
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"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7",
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"er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7"
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};
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static const char *cregnames[] =
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{
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"ccr", "exr", "mach", "macl", "", "", "vbr", "sbr"
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};
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static void
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print_one_arg (disassemble_info *info,
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bfd_vma addr,
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op_type x,
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int cst,
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int cstlen,
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int rdisp_n,
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int rn,
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const char **pregnames,
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int len)
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{
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void * stream = info->stream;
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fprintf_ftype outfn = info->fprintf_func;
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if ((x & SIZE) == L_3 || (x & SIZE) == L_3NZ)
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outfn (stream, "#0x%x", (unsigned) cst);
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else if ((x & MODE) == IMM)
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outfn (stream, "#0x%x", (unsigned) cst);
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else if ((x & MODE) == DBIT || (x & MODE) == KBIT)
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outfn (stream, "#%d", (unsigned) cst);
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else if ((x & MODE) == CONST_2)
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outfn (stream, "#2");
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else if ((x & MODE) == CONST_4)
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outfn (stream, "#4");
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else if ((x & MODE) == CONST_8)
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outfn (stream, "#8");
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else if ((x & MODE) == CONST_16)
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outfn (stream, "#16");
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else if ((x & MODE) == REG)
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{
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switch (x & SIZE)
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{
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case L_8:
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outfn (stream, "%s", regnames[rn]);
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break;
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case L_16:
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case L_16U:
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outfn (stream, "%s", wregnames[rn]);
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break;
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case L_P:
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case L_32:
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outfn (stream, "%s", lregnames[rn]);
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break;
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}
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}
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else if ((x & MODE) == LOWREG)
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{
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switch (x & SIZE)
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{
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case L_8:
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/* Always take low half of reg. */
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outfn (stream, "%s.b", regnames[rn < 8 ? rn + 8 : rn]);
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break;
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case L_16:
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case L_16U:
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/* Always take low half of reg. */
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outfn (stream, "%s.w", wregnames[rn < 8 ? rn : rn - 8]);
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break;
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case L_P:
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case L_32:
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outfn (stream, "%s.l", lregnames[rn]);
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break;
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}
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}
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else if ((x & MODE) == POSTINC)
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outfn (stream, "@%s+", pregnames[rn]);
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else if ((x & MODE) == POSTDEC)
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outfn (stream, "@%s-", pregnames[rn]);
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else if ((x & MODE) == PREINC)
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outfn (stream, "@+%s", pregnames[rn]);
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else if ((x & MODE) == PREDEC)
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outfn (stream, "@-%s", pregnames[rn]);
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else if ((x & MODE) == IND)
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outfn (stream, "@%s", pregnames[rn]);
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else if ((x & MODE) == ABS || (x & ABSJMP))
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outfn (stream, "@0x%x:%d", (unsigned) cst, cstlen);
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else if ((x & MODE) == MEMIND)
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outfn (stream, "@@%d (0x%x)", cst, cst);
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else if ((x & MODE) == VECIND)
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{
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/* FIXME Multiplier should be 2 or 4, depending on processor mode,
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by which is meant "normal" vs. "middle", "advanced", "maximum". */
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int offset = (cst + 0x80) * 4;
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outfn (stream, "@@%d (0x%x)", offset, offset);
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}
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else if ((x & MODE) == PCREL)
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{
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if ((x & SIZE) == L_16 ||
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(x & SIZE) == L_16U)
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{
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outfn (stream, ".%s%d (0x%lx)",
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(short) cst > 0 ? "+" : "",
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(short) cst,
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(long)(addr + (short) cst + len));
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}
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else
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{
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outfn (stream, ".%s%d (0x%lx)",
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(char) cst > 0 ? "+" : "",
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(char) cst,
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(long)(addr + (char) cst + len));
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}
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}
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else if ((x & MODE) == DISP)
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outfn (stream, "@(0x%x:%d,%s)", cst, cstlen, pregnames[rdisp_n]);
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else if ((x & MODE) == INDEXB)
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/* Always take low half of reg. */
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outfn (stream, "@(0x%x:%d,%s.b)", cst, cstlen,
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regnames[rdisp_n < 8 ? rdisp_n + 8 : rdisp_n]);
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else if ((x & MODE) == INDEXW)
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/* Always take low half of reg. */
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outfn (stream, "@(0x%x:%d,%s.w)", cst, cstlen,
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wregnames[rdisp_n < 8 ? rdisp_n : rdisp_n - 8]);
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else if ((x & MODE) == INDEXL)
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outfn (stream, "@(0x%x:%d,%s.l)", cst, cstlen, lregnames[rdisp_n]);
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else if (x & CTRL)
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outfn (stream, "%s", cregnames[rn]);
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else if ((x & MODE) == CCR)
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outfn (stream, "ccr");
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else if ((x & MODE) == EXR)
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outfn (stream, "exr");
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else if ((x & MODE) == MACREG)
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outfn (stream, "mac%c", cst ? 'l' : 'h');
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else
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/* xgettext:c-format */
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outfn (stream, _("Hmmmm 0x%x"), x);
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}
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static unsigned int
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bfd_h8_disassemble (bfd_vma addr, disassemble_info *info, int mach)
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{
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/* Find the first entry in the table for this opcode. */
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int regno[3] = { 0, 0, 0 };
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int dispregno[3] = { 0, 0, 0 };
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int cst[3] = { 0, 0, 0 };
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int cstlen[3] = { 0, 0, 0 };
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static bfd_boolean init = 0;
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const struct h8_instruction *qi;
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char const **pregnames = mach != 0 ? lregnames : wregnames;
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int status;
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unsigned int l;
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unsigned char data[MAX_CODE_NIBBLES];
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void *stream = info->stream;
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fprintf_ftype outfn = info->fprintf_func;
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if (!init)
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{
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bfd_h8_disassemble_init ();
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init = 1;
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}
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status = info->read_memory_func (addr, data, 2, info);
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if (status != 0)
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{
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info->memory_error_func (status, addr, info);
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return -1;
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}
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for (l = 2; status == 0 && l < sizeof (data) / 2; l += 2)
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status = info->read_memory_func (addr + l, data + l, 2, info);
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/* Find the exact opcode/arg combo. */
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for (qi = h8_instructions; qi->opcode->name; qi++)
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{
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const struct h8_opcode *q = qi->opcode;
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const op_type *nib = q->data.nib;
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unsigned int len = 0;
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while (1)
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{
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op_type looking_for = *nib;
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int thisnib = data[len / 2];
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int opnr;
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thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib / 16) & 0xf);
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opnr = ((looking_for & OP3) == OP3 ? 2
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: (looking_for & DST) == DST ? 1 : 0);
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if (looking_for < 16 && looking_for >= 0)
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{
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if (looking_for != thisnib)
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goto fail;
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}
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else
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{
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if ((int) looking_for & (int) B31)
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{
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if (!((thisnib & 0x8) != 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B31);
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thisnib &= 0x7;
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}
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else if ((int) looking_for & (int) B30)
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{
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if (!((thisnib & 0x8) == 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B30);
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}
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if ((int) looking_for & (int) B21)
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{
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if (!((thisnib & 0x4) != 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B21);
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thisnib &= 0xb;
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}
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else if ((int) looking_for & (int) B20)
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{
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if (!((thisnib & 0x4) == 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B20);
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}
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if ((int) looking_for & (int) B11)
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{
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if (!((thisnib & 0x2) != 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B11);
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thisnib &= 0xd;
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}
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else if ((int) looking_for & (int) B10)
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{
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if (!((thisnib & 0x2) == 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B10);
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}
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if ((int) looking_for & (int) B01)
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{
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if (!((thisnib & 0x1) != 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B01);
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thisnib &= 0xe;
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}
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else if ((int) looking_for & (int) B00)
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{
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if (!((thisnib & 0x1) == 0))
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goto fail;
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looking_for = (op_type) ((int) looking_for & ~(int) B00);
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}
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if (looking_for & IGNORE)
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{
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/* Hitachi has declared that IGNORE must be zero. */
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if (thisnib != 0)
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goto fail;
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}
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else if ((looking_for & MODE) == DATA)
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{
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; /* Skip embedded data. */
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}
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else if ((looking_for & MODE) == DBIT)
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{
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/* Exclude adds/subs by looking at bit 0 and 2, and
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make sure the operand size, either w or l,
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matches by looking at bit 1. */
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if ((looking_for & 7) != (thisnib & 7))
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goto fail;
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cst[opnr] = (thisnib & 0x8) ? 2 : 1;
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}
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else if ((looking_for & MODE) == DISP
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|| (looking_for & MODE) == ABS
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|| (looking_for & MODE) == PCREL
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|| (looking_for & MODE) == INDEXB
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|| (looking_for & MODE) == INDEXW
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|| (looking_for & MODE) == INDEXL)
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{
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extract_immediate (stream, looking_for, thisnib,
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data + len / 2, cst + opnr,
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cstlen + opnr, q);
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/* Even address == bra, odd == bra/s. */
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if (q->how == O (O_BRAS, SB))
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cst[opnr] -= 1;
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}
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else if ((looking_for & MODE) == REG
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|| (looking_for & MODE) == LOWREG
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|| (looking_for & MODE) == IND
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|| (looking_for & MODE) == PREINC
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|| (looking_for & MODE) == POSTINC
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|| (looking_for & MODE) == PREDEC
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|| (looking_for & MODE) == POSTDEC)
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{
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regno[opnr] = thisnib;
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}
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else if (looking_for & CTRL) /* Control Register. */
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{
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thisnib &= 7;
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if (((looking_for & MODE) == CCR && (thisnib != C_CCR))
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|| ((looking_for & MODE) == EXR && (thisnib != C_EXR))
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|| ((looking_for & MODE) == MACH && (thisnib != C_MACH))
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|| ((looking_for & MODE) == MACL && (thisnib != C_MACL))
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|| ((looking_for & MODE) == VBR && (thisnib != C_VBR))
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|| ((looking_for & MODE) == SBR && (thisnib != C_SBR)))
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goto fail;
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if (((looking_for & MODE) == CCR_EXR
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&& (thisnib != C_CCR && thisnib != C_EXR))
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|| ((looking_for & MODE) == VBR_SBR
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&& (thisnib != C_VBR && thisnib != C_SBR))
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|| ((looking_for & MODE) == MACREG
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&& (thisnib != C_MACH && thisnib != C_MACL)))
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|
goto fail;
|
|
if (((looking_for & MODE) == CC_EX_VB_SB
|
|
&& (thisnib != C_CCR && thisnib != C_EXR
|
|
&& thisnib != C_VBR && thisnib != C_SBR)))
|
|
goto fail;
|
|
|
|
regno[opnr] = thisnib;
|
|
}
|
|
else if ((looking_for & SIZE) == L_5)
|
|
{
|
|
cst[opnr] = data[len / 2] & 31;
|
|
cstlen[opnr] = 5;
|
|
}
|
|
else if ((looking_for & SIZE) == L_4)
|
|
{
|
|
cst[opnr] = thisnib;
|
|
cstlen[opnr] = 4;
|
|
}
|
|
else if ((looking_for & SIZE) == L_16
|
|
|| (looking_for & SIZE) == L_16U)
|
|
{
|
|
cst[opnr] = (data[len / 2]) * 256 + data[(len + 2) / 2];
|
|
cstlen[opnr] = 16;
|
|
}
|
|
else if ((looking_for & MODE) == MEMIND)
|
|
{
|
|
cst[opnr] = data[1];
|
|
}
|
|
else if ((looking_for & MODE) == VECIND)
|
|
{
|
|
cst[opnr] = data[1] & 0x7f;
|
|
}
|
|
else if ((looking_for & SIZE) == L_32)
|
|
{
|
|
int i = len / 2;
|
|
|
|
cst[opnr] = (((unsigned) data[i] << 24)
|
|
| (data[i + 1] << 16)
|
|
| (data[i + 2] << 8)
|
|
| (data[i + 3]));
|
|
|
|
cstlen[opnr] = 32;
|
|
}
|
|
else if ((looking_for & SIZE) == L_24)
|
|
{
|
|
int i = len / 2;
|
|
|
|
cst[opnr] =
|
|
(data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]);
|
|
cstlen[opnr] = 24;
|
|
}
|
|
else if (looking_for & DISPREG)
|
|
{
|
|
dispregno[opnr] = thisnib & 7;
|
|
}
|
|
else if ((looking_for & MODE) == KBIT)
|
|
{
|
|
switch (thisnib)
|
|
{
|
|
case 9:
|
|
cst[opnr] = 4;
|
|
break;
|
|
case 8:
|
|
cst[opnr] = 2;
|
|
break;
|
|
case 0:
|
|
cst[opnr] = 1;
|
|
break;
|
|
default:
|
|
goto fail;
|
|
}
|
|
}
|
|
else if ((looking_for & SIZE) == L_8)
|
|
{
|
|
cstlen[opnr] = 8;
|
|
cst[opnr] = data[len / 2];
|
|
}
|
|
else if ((looking_for & SIZE) == L_3
|
|
|| (looking_for & SIZE) == L_3NZ)
|
|
{
|
|
cst[opnr] = thisnib & 0x7;
|
|
if (cst[opnr] == 0 && (looking_for & SIZE) == L_3NZ)
|
|
goto fail;
|
|
}
|
|
else if ((looking_for & SIZE) == L_2)
|
|
{
|
|
cstlen[opnr] = 2;
|
|
cst[opnr] = thisnib & 0x3;
|
|
}
|
|
else if ((looking_for & MODE) == MACREG)
|
|
{
|
|
cst[opnr] = (thisnib == 3);
|
|
}
|
|
else if (looking_for == (op_type) E)
|
|
{
|
|
outfn (stream, "%s\t", q->name);
|
|
|
|
/* Gross. Disgusting. */
|
|
if (strcmp (q->name, "ldm.l") == 0)
|
|
{
|
|
int count, high;
|
|
|
|
count = (data[1] / 16) & 0x3;
|
|
high = regno[1];
|
|
|
|
outfn (stream, "@sp+,er%d-er%d", high - count, high);
|
|
return qi->length;
|
|
}
|
|
|
|
if (strcmp (q->name, "stm.l") == 0)
|
|
{
|
|
int count, low;
|
|
|
|
count = (data[1] / 16) & 0x3;
|
|
low = regno[0];
|
|
|
|
outfn (stream, "er%d-er%d,@-sp", low, low + count);
|
|
return qi->length;
|
|
}
|
|
if (strcmp (q->name, "rte/l") == 0
|
|
|| strcmp (q->name, "rts/l") == 0)
|
|
{
|
|
if (regno[0] == 0)
|
|
outfn (stream, "er%d", regno[1]);
|
|
else
|
|
outfn (stream, "er%d-er%d", regno[1] - regno[0],
|
|
regno[1]);
|
|
return qi->length;
|
|
}
|
|
if (CONST_STRNEQ (q->name, "mova"))
|
|
{
|
|
const op_type *args = q->args.nib;
|
|
|
|
if (args[1] == (op_type) E)
|
|
{
|
|
/* Short form. */
|
|
print_one_arg (info, addr, args[0], cst[0],
|
|
cstlen[0], dispregno[0], regno[0],
|
|
pregnames, qi->length);
|
|
outfn (stream, ",er%d", dispregno[0]);
|
|
}
|
|
else
|
|
{
|
|
outfn (stream, "@(0x%x:%d,", cst[0], cstlen[0]);
|
|
print_one_arg (info, addr, args[1], cst[1],
|
|
cstlen[1], dispregno[1], regno[1],
|
|
pregnames, qi->length);
|
|
outfn (stream, ".%c),",
|
|
(args[0] & MODE) == INDEXB ? 'b' : 'w');
|
|
print_one_arg (info, addr, args[2], cst[2],
|
|
cstlen[2], dispregno[2], regno[2],
|
|
pregnames, qi->length);
|
|
}
|
|
return qi->length;
|
|
}
|
|
/* Fill in the args. */
|
|
{
|
|
const op_type *args = q->args.nib;
|
|
int hadone = 0;
|
|
int nargs;
|
|
|
|
/* Special case handling for the adds and subs instructions
|
|
since in H8 mode thay can only take the r0-r7 registers
|
|
but in other (higher) modes they can take the er0-er7
|
|
registers as well. */
|
|
if (strcmp (qi->opcode->name, "adds") == 0
|
|
|| strcmp (qi->opcode->name, "subs") == 0)
|
|
{
|
|
outfn (stream, "#%d,%s", cst[0], pregnames[regno[1] & 0x7]);
|
|
return qi->length;
|
|
}
|
|
|
|
for (nargs = 0;
|
|
nargs < 3 && args[nargs] != (op_type) E;
|
|
nargs++)
|
|
{
|
|
int x = args[nargs];
|
|
|
|
if (hadone)
|
|
outfn (stream, ",");
|
|
|
|
print_one_arg (info, addr, x,
|
|
cst[nargs], cstlen[nargs],
|
|
dispregno[nargs], regno[nargs],
|
|
pregnames, qi->length);
|
|
|
|
hadone = 1;
|
|
}
|
|
}
|
|
|
|
return qi->length;
|
|
}
|
|
else
|
|
/* xgettext:c-format */
|
|
outfn (stream, _("Don't understand 0x%x \n"), looking_for);
|
|
}
|
|
|
|
len++;
|
|
nib++;
|
|
}
|
|
|
|
fail:
|
|
;
|
|
}
|
|
|
|
/* Fell off the end. */
|
|
outfn (stream, ".word\tH'%x,H'%x", data[0], data[1]);
|
|
return 2;
|
|
}
|
|
|
|
int
|
|
print_insn_h8300 (bfd_vma addr, disassemble_info *info)
|
|
{
|
|
return bfd_h8_disassemble (addr, info, 0);
|
|
}
|
|
|
|
int
|
|
print_insn_h8300h (bfd_vma addr, disassemble_info *info)
|
|
{
|
|
return bfd_h8_disassemble (addr, info, 1);
|
|
}
|
|
|
|
int
|
|
print_insn_h8300s (bfd_vma addr, disassemble_info *info)
|
|
{
|
|
return bfd_h8_disassemble (addr, info, 2);
|
|
}
|