mirror of
https://sourceware.org/git/binutils-gdb.git
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1252 lines
32 KiB
C
1252 lines
32 KiB
C
/* Disassembler for the PA-RISC. Somewhat derived from sparc-pinsn.c.
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Copyright 1989, 1990, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2003
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Free Software Foundation, Inc.
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Contributed by the Center for Software Science at the
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University of Utah (pa-gdb-bugs@cs.utah.edu).
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "libhppa.h"
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#include "opcode/hppa.h"
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/* Integer register names, indexed by the numbers which appear in the
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opcodes. */
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static const char *const reg_names[] =
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{"flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
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"r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19",
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"r20", "r21", "r22", "r23", "r24", "r25", "r26", "dp", "ret0", "ret1",
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"sp", "r31"};
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/* Floating point register names, indexed by the numbers which appear in the
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opcodes. */
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static const char *const fp_reg_names[] =
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{"fpsr", "fpe2", "fpe4", "fpe6",
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"fr4", "fr5", "fr6", "fr7", "fr8",
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"fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
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"fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
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"fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31"};
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typedef unsigned int CORE_ADDR;
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/* Get at various relevent fields of an instruction word. */
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#define MASK_5 0x1f
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#define MASK_10 0x3ff
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#define MASK_11 0x7ff
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#define MASK_14 0x3fff
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#define MASK_16 0xffff
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#define MASK_21 0x1fffff
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/* These macros get bit fields using HP's numbering (MSB = 0) */
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#define GET_FIELD(X, FROM, TO) \
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((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
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#define GET_BIT(X, WHICH) \
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GET_FIELD (X, WHICH, WHICH)
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/* Some of these have been converted to 2-d arrays because they
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consume less storage this way. If the maintenance becomes a
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problem, convert them back to const 1-d pointer arrays. */
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static const char *const control_reg[] = {
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"rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
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"pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4",
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"iva", "eiem", "itmr", "pcsq", "pcoq", "iir", "isr",
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"ior", "ipsw", "eirr", "tr0", "tr1", "tr2", "tr3",
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"tr4", "tr5", "tr6", "tr7"
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};
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static const char *const compare_cond_names[] = {
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"", ",=", ",<", ",<=", ",<<", ",<<=", ",sv", ",od",
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",tr", ",<>", ",>=", ",>", ",>>=", ",>>", ",nsv", ",ev"
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};
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static const char *const compare_cond_64_names[] = {
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"", ",*=", ",*<", ",*<=", ",*<<", ",*<<=", ",*sv", ",*od",
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",*tr", ",*<>", ",*>=", ",*>", ",*>>=", ",*>>", ",*nsv", ",*ev"
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};
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static const char *const cmpib_cond_64_names[] = {
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",*<<", ",*=", ",*<", ",*<=", ",*>>=", ",*<>", ",*>=", ",*>"
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};
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static const char *const add_cond_names[] = {
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"", ",=", ",<", ",<=", ",nuv", ",znv", ",sv", ",od",
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",tr", ",<>", ",>=", ",>", ",uv", ",vnz", ",nsv", ",ev"
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};
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static const char *const add_cond_64_names[] = {
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"", ",*=", ",*<", ",*<=", ",*nuv", ",*znv", ",*sv", ",*od",
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",*tr", ",*<>", ",*>=", ",*>", ",*uv", ",*vnz", ",*nsv", ",*ev"
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};
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static const char *const wide_add_cond_names[] = {
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"", ",=", ",<", ",<=", ",nuv", ",*=", ",*<", ",*<=",
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",tr", ",<>", ",>=", ",>", ",uv", ",*<>", ",*>=", ",*>"
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};
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static const char *const logical_cond_names[] = {
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"", ",=", ",<", ",<=", 0, 0, 0, ",od",
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",tr", ",<>", ",>=", ",>", 0, 0, 0, ",ev"};
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static const char *const logical_cond_64_names[] = {
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"", ",*=", ",*<", ",*<=", 0, 0, 0, ",*od",
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",*tr", ",*<>", ",*>=", ",*>", 0, 0, 0, ",*ev"};
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static const char *const unit_cond_names[] = {
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"", ",swz", ",sbz", ",shz", ",sdc", ",swc", ",sbc", ",shc",
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",tr", ",nwz", ",nbz", ",nhz", ",ndc", ",nwc", ",nbc", ",nhc"
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};
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static const char *const unit_cond_64_names[] = {
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"", ",*swz", ",*sbz", ",*shz", ",*sdc", ",*swc", ",*sbc", ",*shc",
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",*tr", ",*nwz", ",*nbz", ",*nhz", ",*ndc", ",*nwc", ",*nbc", ",*nhc"
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};
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static const char *const shift_cond_names[] = {
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"", ",=", ",<", ",od", ",tr", ",<>", ",>=", ",ev"
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};
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static const char *const shift_cond_64_names[] = {
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"", ",*=", ",*<", ",*od", ",*tr", ",*<>", ",*>=", ",*ev"
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};
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static const char *const bb_cond_64_names[] = {
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",*<", ",*>="
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};
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static const char *const index_compl_names[] = {"", ",m", ",s", ",sm"};
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static const char *const short_ldst_compl_names[] = {"", ",ma", "", ",mb"};
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static const char *const short_bytes_compl_names[] = {
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"", ",b,m", ",e", ",e,m"
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};
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static const char *const float_format_names[] = {",sgl", ",dbl", "", ",quad"};
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static const char *const fcnv_fixed_names[] = {",w", ",dw", "", ",qw"};
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static const char *const fcnv_ufixed_names[] = {",uw", ",udw", "", ",uqw"};
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static const char *const float_comp_names[] =
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{
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",false?", ",false", ",?", ",!<=>", ",=", ",=t", ",?=", ",!<>",
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",!?>=", ",<", ",?<", ",!>=", ",!?>", ",<=", ",?<=", ",!>",
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",!?<=", ",>", ",?>", ",!<=", ",!?<", ",>=", ",?>=", ",!<",
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",!?=", ",<>", ",!=", ",!=t", ",!?", ",<=>", ",true?", ",true"
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};
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static const char *const signed_unsigned_names[] = {",u", ",s"};
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static const char *const mix_half_names[] = {",l", ",r"};
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static const char *const saturation_names[] = {",us", ",ss", 0, ""};
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static const char *const read_write_names[] = {",r", ",w"};
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static const char *const add_compl_names[] = { 0, "", ",l", ",tsv" };
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/* For a bunch of different instructions form an index into a
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completer name table. */
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#define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \
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GET_FIELD (insn, 18, 18) << 1)
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#define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \
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(GET_FIELD ((insn), 19, 19) ? 8 : 0))
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static void fput_reg PARAMS ((unsigned int, disassemble_info *));
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static void fput_fp_reg PARAMS ((unsigned int, disassemble_info *));
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static void fput_fp_reg_r PARAMS ((unsigned int, disassemble_info *));
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static void fput_creg PARAMS ((unsigned int, disassemble_info *));
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static void fput_const PARAMS ((unsigned int, disassemble_info *));
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static int extract_3 PARAMS ((unsigned int));
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static int extract_5_load PARAMS ((unsigned int));
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static int extract_5_store PARAMS ((unsigned int));
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static unsigned extract_5r_store PARAMS ((unsigned int));
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static unsigned extract_5R_store PARAMS ((unsigned int));
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static unsigned extract_10U_store PARAMS ((unsigned int));
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static unsigned extract_5Q_store PARAMS ((unsigned int));
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static int extract_11 PARAMS ((unsigned int));
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static int extract_14 PARAMS ((unsigned int));
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static int extract_16 PARAMS ((unsigned int));
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static int extract_21 PARAMS ((unsigned int));
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static int extract_12 PARAMS ((unsigned int));
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static int extract_17 PARAMS ((unsigned int));
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static int extract_22 PARAMS ((unsigned int));
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/* Utility function to print registers. Put these first, so gcc's function
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inlining can do its stuff. */
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#define fputs_filtered(STR,F) (*info->fprintf_func) (info->stream, "%s", STR)
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static void
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fput_reg (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, reg ? reg_names[reg] : "r0");
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}
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static void
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fput_fp_reg (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, reg ? fp_reg_names[reg] : "fr0");
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}
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static void
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fput_fp_reg_r (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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/* Special case floating point exception registers. */
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if (reg < 4)
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(*info->fprintf_func) (info->stream, "fpe%d", reg * 2 + 1);
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else
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(*info->fprintf_func) (info->stream, "%sR",
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reg ? fp_reg_names[reg] : "fr0");
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}
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static void
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fput_creg (reg, info)
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unsigned reg;
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disassemble_info *info;
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{
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(*info->fprintf_func) (info->stream, control_reg[reg]);
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}
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/* Print constants with sign. */
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static void
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fput_const (num, info)
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unsigned num;
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disassemble_info *info;
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{
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if ((int)num < 0)
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(*info->fprintf_func) (info->stream, "-%x", -(int)num);
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else
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(*info->fprintf_func) (info->stream, "%x", num);
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}
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/* Routines to extract various sized constants out of hppa
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instructions. */
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/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */
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static int
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extract_3 (word)
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unsigned word;
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{
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return GET_FIELD (word, 18, 18) << 2 | GET_FIELD (word, 16, 17);
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}
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static int
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extract_5_load (word)
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unsigned word;
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{
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return low_sign_extend (word >> 16 & MASK_5, 5);
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}
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/* Extract the immediate field from a st{bhw}s instruction. */
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static int
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extract_5_store (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_5, 5);
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}
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/* Extract the immediate field from a break instruction. */
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static unsigned
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extract_5r_store (word)
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unsigned word;
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{
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return (word & MASK_5);
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}
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/* Extract the immediate field from a {sr}sm instruction. */
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static unsigned
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extract_5R_store (word)
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unsigned word;
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{
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return (word >> 16 & MASK_5);
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}
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/* Extract the 10 bit immediate field from a {sr}sm instruction. */
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static unsigned
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extract_10U_store (word)
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unsigned word;
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{
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return (word >> 16 & MASK_10);
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}
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/* Extract the immediate field from a bb instruction. */
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static unsigned
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extract_5Q_store (word)
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unsigned word;
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{
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return (word >> 21 & MASK_5);
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}
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/* Extract an 11 bit immediate field. */
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static int
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extract_11 (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_11, 11);
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}
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/* Extract a 14 bit immediate field. */
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static int
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extract_14 (word)
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unsigned word;
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{
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return low_sign_extend (word & MASK_14, 14);
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}
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/* Extract a 16 bit immediate field (PA2.0 wide only). */
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static int
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extract_16 (word)
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unsigned word;
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{
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int m15, m0, m1;
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m0 = GET_BIT (word, 16);
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m1 = GET_BIT (word, 17);
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m15 = GET_BIT (word, 31);
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word = (word >> 1) & 0x1fff;
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word = word | (m15 << 15) | ((m15 ^ m0) << 14) | ((m15 ^ m1) << 13);
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return sign_extend (word, 16);
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}
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/* Extract a 21 bit constant. */
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static int
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extract_21 (word)
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unsigned word;
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{
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int val;
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word &= MASK_21;
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word <<= 11;
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val = GET_FIELD (word, 20, 20);
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val <<= 11;
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val |= GET_FIELD (word, 9, 19);
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val <<= 2;
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val |= GET_FIELD (word, 5, 6);
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val <<= 5;
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val |= GET_FIELD (word, 0, 4);
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val <<= 2;
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val |= GET_FIELD (word, 7, 8);
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return sign_extend (val, 21) << 11;
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}
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/* Extract a 12 bit constant from branch instructions. */
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static int
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extract_12 (word)
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unsigned word;
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{
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return sign_extend (GET_FIELD (word, 19, 28) |
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GET_FIELD (word, 29, 29) << 10 |
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(word & 0x1) << 11, 12) << 2;
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}
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/* Extract a 17 bit constant from branch instructions, returning the
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19 bit signed value. */
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static int
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extract_17 (word)
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unsigned word;
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{
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return sign_extend (GET_FIELD (word, 19, 28) |
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GET_FIELD (word, 29, 29) << 10 |
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GET_FIELD (word, 11, 15) << 11 |
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(word & 0x1) << 16, 17) << 2;
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}
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static int
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extract_22 (word)
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unsigned word;
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{
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return sign_extend (GET_FIELD (word, 19, 28) |
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GET_FIELD (word, 29, 29) << 10 |
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GET_FIELD (word, 11, 15) << 11 |
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GET_FIELD (word, 6, 10) << 16 |
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(word & 0x1) << 21, 22) << 2;
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}
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/* Print one instruction. */
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int
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print_insn_hppa (memaddr, info)
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bfd_vma memaddr;
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disassemble_info *info;
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{
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bfd_byte buffer[4];
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unsigned int insn, i;
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{
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int status =
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(*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
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if (status != 0)
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{
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(*info->memory_error_func) (status, memaddr, info);
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return -1;
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}
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}
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insn = bfd_getb32 (buffer);
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for (i = 0; i < NUMOPCODES; ++i)
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{
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const struct pa_opcode *opcode = &pa_opcodes[i];
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if ((insn & opcode->mask) == opcode->match)
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{
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register const char *s;
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#ifndef BFD64
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if (opcode->arch == pa20w)
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continue;
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#endif
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
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|
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if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
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(*info->fprintf_func) (info->stream, " ");
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for (s = opcode->args; *s != '\0'; ++s)
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{
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switch (*s)
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{
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case 'x':
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fput_reg (GET_FIELD (insn, 11, 15), info);
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break;
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case 'a':
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case 'b':
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fput_reg (GET_FIELD (insn, 6, 10), info);
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break;
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case '^':
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fput_creg (GET_FIELD (insn, 6, 10), info);
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break;
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case 't':
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fput_reg (GET_FIELD (insn, 27, 31), info);
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break;
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/* Handle floating point registers. */
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case 'f':
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switch (*++s)
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{
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case 't':
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fput_fp_reg (GET_FIELD (insn, 27, 31), info);
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break;
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case 'T':
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if (GET_FIELD (insn, 25, 25))
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fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
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else
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fput_fp_reg (GET_FIELD (insn, 27, 31), info);
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break;
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case 'a':
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if (GET_FIELD (insn, 25, 25))
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fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
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else
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fput_fp_reg (GET_FIELD (insn, 6, 10), info);
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break;
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/* 'fA' will not generate a space before the regsiter
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name. Normally that is fine. Except that it
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causes problems with xmpyu which has no FP format
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|
completer. */
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case 'X':
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fputs_filtered (" ", info);
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/* FALLTHRU */
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case 'A':
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if (GET_FIELD (insn, 24, 24))
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fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
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else
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fput_fp_reg (GET_FIELD (insn, 6, 10), info);
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break;
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case 'b':
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if (GET_FIELD (insn, 25, 25))
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fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
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else
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fput_fp_reg (GET_FIELD (insn, 11, 15), info);
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break;
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case 'B':
|
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if (GET_FIELD (insn, 19, 19))
|
|
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
|
|
else
|
|
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
|
|
break;
|
|
case 'C':
|
|
{
|
|
int reg = GET_FIELD (insn, 21, 22);
|
|
reg |= GET_FIELD (insn, 16, 18) << 2;
|
|
if (GET_FIELD (insn, 23, 23) != 0)
|
|
fput_fp_reg_r (reg, info);
|
|
else
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
case 'i':
|
|
{
|
|
int reg = GET_FIELD (insn, 6, 10);
|
|
|
|
reg |= (GET_FIELD (insn, 26, 26) << 4);
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
case 'j':
|
|
{
|
|
int reg = GET_FIELD (insn, 11, 15);
|
|
|
|
reg |= (GET_FIELD (insn, 26, 26) << 4);
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
case 'k':
|
|
{
|
|
int reg = GET_FIELD (insn, 27, 31);
|
|
|
|
reg |= (GET_FIELD (insn, 26, 26) << 4);
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
case 'l':
|
|
{
|
|
int reg = GET_FIELD (insn, 21, 25);
|
|
|
|
reg |= (GET_FIELD (insn, 26, 26) << 4);
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
case 'm':
|
|
{
|
|
int reg = GET_FIELD (insn, 16, 20);
|
|
|
|
reg |= (GET_FIELD (insn, 26, 26) << 4);
|
|
fput_fp_reg (reg, info);
|
|
break;
|
|
}
|
|
|
|
/* 'fe' will not generate a space before the register
|
|
name. Normally that is fine. Except that it
|
|
causes problems with fstw fe,y(b) which has no FP
|
|
format completer. */
|
|
case 'E':
|
|
fputs_filtered (" ", info);
|
|
/* FALLTHRU */
|
|
|
|
case 'e':
|
|
if (GET_FIELD (insn, 30, 30))
|
|
fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
|
|
else
|
|
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
|
|
break;
|
|
case 'x':
|
|
fput_fp_reg (GET_FIELD (insn, 11, 15), info);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case '5':
|
|
fput_const (extract_5_load (insn), info);
|
|
break;
|
|
case 's':
|
|
{
|
|
int space = GET_FIELD (insn, 16, 17);
|
|
/* Zero means implicit addressing, not use of sr0. */
|
|
if (space != 0)
|
|
(*info->fprintf_func) (info->stream, "sr%d", space);
|
|
}
|
|
break;
|
|
|
|
case 'S':
|
|
(*info->fprintf_func) (info->stream, "sr%d",
|
|
extract_3 (insn));
|
|
break;
|
|
|
|
/* Handle completers. */
|
|
case 'c':
|
|
switch (*++s)
|
|
{
|
|
case 'x':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
index_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 'X':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
index_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 'm':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
short_ldst_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 'M':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
short_ldst_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 'A':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
short_bytes_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 's':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
short_bytes_compl_names[GET_COMPL (insn)]);
|
|
break;
|
|
case 'c':
|
|
case 'C':
|
|
switch (GET_FIELD (insn, 20, 21))
|
|
{
|
|
case 1:
|
|
(*info->fprintf_func) (info->stream, ",bc ");
|
|
break;
|
|
case 2:
|
|
(*info->fprintf_func) (info->stream, ",sl ");
|
|
break;
|
|
default:
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
}
|
|
break;
|
|
case 'd':
|
|
switch (GET_FIELD (insn, 20, 21))
|
|
{
|
|
case 1:
|
|
(*info->fprintf_func) (info->stream, ",co ");
|
|
break;
|
|
default:
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
}
|
|
break;
|
|
case 'o':
|
|
(*info->fprintf_func) (info->stream, ",o");
|
|
break;
|
|
case 'g':
|
|
(*info->fprintf_func) (info->stream, ",gate");
|
|
break;
|
|
case 'p':
|
|
(*info->fprintf_func) (info->stream, ",l,push");
|
|
break;
|
|
case 'P':
|
|
(*info->fprintf_func) (info->stream, ",pop");
|
|
break;
|
|
case 'l':
|
|
case 'L':
|
|
(*info->fprintf_func) (info->stream, ",l");
|
|
break;
|
|
case 'w':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
read_write_names[GET_FIELD (insn, 25, 25)]);
|
|
break;
|
|
case 'W':
|
|
(*info->fprintf_func) (info->stream, ",w");
|
|
break;
|
|
case 'r':
|
|
if (GET_FIELD (insn, 23, 26) == 5)
|
|
(*info->fprintf_func) (info->stream, ",r");
|
|
break;
|
|
case 'Z':
|
|
if (GET_FIELD (insn, 26, 26))
|
|
(*info->fprintf_func) (info->stream, ",m ");
|
|
else
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'i':
|
|
if (GET_FIELD (insn, 25, 25))
|
|
(*info->fprintf_func) (info->stream, ",i");
|
|
break;
|
|
case 'z':
|
|
if (!GET_FIELD (insn, 21, 21))
|
|
(*info->fprintf_func) (info->stream, ",z");
|
|
break;
|
|
case 'a':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
add_compl_names[GET_FIELD (insn, 20, 21)]);
|
|
break;
|
|
case 'Y':
|
|
(*info->fprintf_func)
|
|
(info->stream, ",dc%s",
|
|
add_compl_names[GET_FIELD (insn, 20, 21)]);
|
|
break;
|
|
case 'y':
|
|
(*info->fprintf_func)
|
|
(info->stream, ",c%s",
|
|
add_compl_names[GET_FIELD (insn, 20, 21)]);
|
|
break;
|
|
case 'v':
|
|
if (GET_FIELD (insn, 20, 20))
|
|
(*info->fprintf_func) (info->stream, ",tsv");
|
|
break;
|
|
case 't':
|
|
(*info->fprintf_func) (info->stream, ",tc");
|
|
if (GET_FIELD (insn, 20, 20))
|
|
(*info->fprintf_func) (info->stream, ",tsv");
|
|
break;
|
|
case 'B':
|
|
(*info->fprintf_func) (info->stream, ",db");
|
|
if (GET_FIELD (insn, 20, 20))
|
|
(*info->fprintf_func) (info->stream, ",tsv");
|
|
break;
|
|
case 'b':
|
|
(*info->fprintf_func) (info->stream, ",b");
|
|
if (GET_FIELD (insn, 20, 20))
|
|
(*info->fprintf_func) (info->stream, ",tsv");
|
|
break;
|
|
case 'T':
|
|
if (GET_FIELD (insn, 25, 25))
|
|
(*info->fprintf_func) (info->stream, ",tc");
|
|
break;
|
|
case 'S':
|
|
/* EXTRD/W has a following condition. */
|
|
if (*(s + 1) == '?')
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
|
|
else
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
|
|
break;
|
|
case 'h':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
mix_half_names[GET_FIELD (insn, 17, 17)]);
|
|
break;
|
|
case 'H':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
saturation_names[GET_FIELD (insn, 24, 25)]);
|
|
break;
|
|
case '*':
|
|
(*info->fprintf_func)
|
|
(info->stream, ",%d%d%d%d ",
|
|
GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
|
|
GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
|
|
break;
|
|
|
|
case 'q':
|
|
{
|
|
int m, a;
|
|
|
|
m = GET_FIELD (insn, 28, 28);
|
|
a = GET_FIELD (insn, 29, 29);
|
|
|
|
if (m && !a)
|
|
fputs_filtered (",ma ", info);
|
|
else if (m && a)
|
|
fputs_filtered (",mb ", info);
|
|
else
|
|
fputs_filtered (" ", info);
|
|
break;
|
|
}
|
|
|
|
case 'J':
|
|
{
|
|
int opc = GET_FIELD (insn, 0, 5);
|
|
|
|
if (opc == 0x16 || opc == 0x1e)
|
|
{
|
|
if (GET_FIELD (insn, 29, 29) == 0)
|
|
fputs_filtered (",ma ", info);
|
|
else
|
|
fputs_filtered (",mb ", info);
|
|
}
|
|
else
|
|
fputs_filtered (" ", info);
|
|
break;
|
|
}
|
|
|
|
case 'e':
|
|
{
|
|
int opc = GET_FIELD (insn, 0, 5);
|
|
|
|
if (opc == 0x13 || opc == 0x1b)
|
|
{
|
|
if (GET_FIELD (insn, 18, 18) == 1)
|
|
fputs_filtered (",mb ", info);
|
|
else
|
|
fputs_filtered (",ma ", info);
|
|
}
|
|
else if (opc == 0x17 || opc == 0x1f)
|
|
{
|
|
if (GET_FIELD (insn, 31, 31) == 1)
|
|
fputs_filtered (",ma ", info);
|
|
else
|
|
fputs_filtered (",mb ", info);
|
|
}
|
|
else
|
|
fputs_filtered (" ", info);
|
|
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
/* Handle conditions. */
|
|
case '?':
|
|
{
|
|
s++;
|
|
switch (*s)
|
|
{
|
|
case 'f':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
float_comp_names[GET_FIELD (insn, 27, 31)]);
|
|
break;
|
|
|
|
/* these four conditions are for the set of instructions
|
|
which distinguish true/false conditions by opcode
|
|
rather than by the 'f' bit (sigh): comb, comib,
|
|
addb, addib */
|
|
case 't':
|
|
fputs_filtered
|
|
(compare_cond_names[GET_FIELD (insn, 16, 18)], info);
|
|
break;
|
|
case 'n':
|
|
fputs_filtered
|
|
(compare_cond_names[GET_FIELD (insn, 16, 18)
|
|
+ GET_FIELD (insn, 4, 4) * 8],
|
|
info);
|
|
break;
|
|
case 'N':
|
|
fputs_filtered
|
|
(compare_cond_64_names[GET_FIELD (insn, 16, 18)
|
|
+ GET_FIELD (insn, 2, 2) * 8],
|
|
info);
|
|
break;
|
|
case 'Q':
|
|
fputs_filtered
|
|
(cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
|
|
info);
|
|
break;
|
|
case '@':
|
|
fputs_filtered
|
|
(add_cond_names[GET_FIELD (insn, 16, 18)
|
|
+ GET_FIELD (insn, 4, 4) * 8],
|
|
info);
|
|
break;
|
|
case 's':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
compare_cond_names[GET_COND (insn)]);
|
|
break;
|
|
case 'S':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
compare_cond_64_names[GET_COND (insn)]);
|
|
break;
|
|
case 'a':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
add_cond_names[GET_COND (insn)]);
|
|
break;
|
|
case 'A':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
add_cond_64_names[GET_COND (insn)]);
|
|
break;
|
|
case 'd':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
add_cond_names[GET_FIELD (insn, 16, 18)]);
|
|
break;
|
|
|
|
case 'W':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
wide_add_cond_names[GET_FIELD (insn, 16, 18) +
|
|
GET_FIELD (insn, 4, 4) * 8]);
|
|
break;
|
|
|
|
case 'l':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
logical_cond_names[GET_COND (insn)]);
|
|
break;
|
|
case 'L':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
logical_cond_64_names[GET_COND (insn)]);
|
|
break;
|
|
case 'u':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
unit_cond_names[GET_COND (insn)]);
|
|
break;
|
|
case 'U':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
unit_cond_64_names[GET_COND (insn)]);
|
|
break;
|
|
case 'y':
|
|
case 'x':
|
|
case 'b':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
shift_cond_names[GET_FIELD (insn, 16, 18)]);
|
|
|
|
/* If the next character in args is 'n', it will handle
|
|
putting out the space. */
|
|
if (s[1] != 'n')
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'X':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
|
|
break;
|
|
case 'B':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s",
|
|
bb_cond_64_names[GET_FIELD (insn, 16, 16)]);
|
|
|
|
/* If the next character in args is 'n', it will handle
|
|
putting out the space. */
|
|
if (s[1] != 'n')
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 'V':
|
|
fput_const (extract_5_store (insn), info);
|
|
break;
|
|
case 'r':
|
|
fput_const (extract_5r_store (insn), info);
|
|
break;
|
|
case 'R':
|
|
fput_const (extract_5R_store (insn), info);
|
|
break;
|
|
case 'U':
|
|
fput_const (extract_10U_store (insn), info);
|
|
break;
|
|
case 'B':
|
|
case 'Q':
|
|
fput_const (extract_5Q_store (insn), info);
|
|
break;
|
|
case 'i':
|
|
fput_const (extract_11 (insn), info);
|
|
break;
|
|
case 'j':
|
|
fput_const (extract_14 (insn), info);
|
|
break;
|
|
case 'k':
|
|
fput_const (extract_21 (insn), info);
|
|
break;
|
|
case '<':
|
|
case 'l':
|
|
/* 16-bit long disp., PA2.0 wide only. */
|
|
fput_const (extract_16 (insn), info);
|
|
break;
|
|
case 'n':
|
|
if (insn & 0x2)
|
|
(*info->fprintf_func) (info->stream, ",n ");
|
|
else
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'N':
|
|
if ((insn & 0x20) && s[1])
|
|
(*info->fprintf_func) (info->stream, ",n ");
|
|
else if (insn & 0x20)
|
|
(*info->fprintf_func) (info->stream, ",n");
|
|
else if (s[1])
|
|
(*info->fprintf_func) (info->stream, " ");
|
|
break;
|
|
case 'w':
|
|
(*info->print_address_func)
|
|
(memaddr + 8 + extract_12 (insn), info);
|
|
break;
|
|
case 'W':
|
|
/* 17 bit PC-relative branch. */
|
|
(*info->print_address_func)
|
|
((memaddr + 8 + extract_17 (insn)), info);
|
|
break;
|
|
case 'z':
|
|
/* 17 bit displacement. This is an offset from a register
|
|
so it gets disasssembled as just a number, not any sort
|
|
of address. */
|
|
fput_const (extract_17 (insn), info);
|
|
break;
|
|
|
|
case 'Z':
|
|
/* addil %r1 implicit output. */
|
|
(*info->fprintf_func) (info->stream, "%%r1");
|
|
break;
|
|
|
|
case 'Y':
|
|
/* be,l %sr0,%r31 implicit output. */
|
|
(*info->fprintf_func) (info->stream, "%%sr0,%%r31");
|
|
break;
|
|
|
|
case '@':
|
|
(*info->fprintf_func) (info->stream, "0");
|
|
break;
|
|
|
|
case '.':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
GET_FIELD (insn, 24, 25));
|
|
break;
|
|
case '*':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
GET_FIELD (insn, 22, 25));
|
|
break;
|
|
case '!':
|
|
(*info->fprintf_func) (info->stream, "%%sar");
|
|
break;
|
|
case 'p':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
31 - GET_FIELD (insn, 22, 26));
|
|
break;
|
|
case '~':
|
|
{
|
|
int num;
|
|
num = GET_FIELD (insn, 20, 20) << 5;
|
|
num |= GET_FIELD (insn, 22, 26);
|
|
(*info->fprintf_func) (info->stream, "%d", 63 - num);
|
|
break;
|
|
}
|
|
case 'P':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
GET_FIELD (insn, 22, 26));
|
|
break;
|
|
case 'q':
|
|
{
|
|
int num;
|
|
num = GET_FIELD (insn, 20, 20) << 5;
|
|
num |= GET_FIELD (insn, 22, 26);
|
|
(*info->fprintf_func) (info->stream, "%d", num);
|
|
break;
|
|
}
|
|
case 'T':
|
|
(*info->fprintf_func) (info->stream, "%d",
|
|
32 - GET_FIELD (insn, 27, 31));
|
|
break;
|
|
case '%':
|
|
{
|
|
int num;
|
|
num = (GET_FIELD (insn, 23, 23) + 1) * 32;
|
|
num -= GET_FIELD (insn, 27, 31);
|
|
(*info->fprintf_func) (info->stream, "%d", num);
|
|
break;
|
|
}
|
|
case '|':
|
|
{
|
|
int num;
|
|
num = (GET_FIELD (insn, 19, 19) + 1) * 32;
|
|
num -= GET_FIELD (insn, 27, 31);
|
|
(*info->fprintf_func) (info->stream, "%d", num);
|
|
break;
|
|
}
|
|
case '$':
|
|
fput_const (GET_FIELD (insn, 20, 28), info);
|
|
break;
|
|
case 'A':
|
|
fput_const (GET_FIELD (insn, 6, 18), info);
|
|
break;
|
|
case 'D':
|
|
fput_const (GET_FIELD (insn, 6, 31), info);
|
|
break;
|
|
case 'v':
|
|
(*info->fprintf_func) (info->stream, ",%d",
|
|
GET_FIELD (insn, 23, 25));
|
|
break;
|
|
case 'O':
|
|
fput_const ((GET_FIELD (insn, 6,20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case 'o':
|
|
fput_const (GET_FIELD (insn, 6, 20), info);
|
|
break;
|
|
case '2':
|
|
fput_const ((GET_FIELD (insn, 6, 22) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case '1':
|
|
fput_const ((GET_FIELD (insn, 11, 20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case '0':
|
|
fput_const ((GET_FIELD (insn, 16, 20) << 5 |
|
|
GET_FIELD (insn, 27, 31)), info);
|
|
break;
|
|
case 'u':
|
|
(*info->fprintf_func) (info->stream, ",%d",
|
|
GET_FIELD (insn, 23, 25));
|
|
break;
|
|
case 'F':
|
|
/* if no destination completer and not before a completer
|
|
for fcmp, need a space here */
|
|
if (s[1] == 'G' || s[1] == '?')
|
|
fputs_filtered
|
|
(float_format_names[GET_FIELD (insn, 19, 20)], info);
|
|
else
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
float_format_names[GET_FIELD (insn, 19, 20)]);
|
|
break;
|
|
case 'G':
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
float_format_names[GET_FIELD (insn, 17, 18)]);
|
|
break;
|
|
case 'H':
|
|
if (GET_FIELD (insn, 26, 26) == 1)
|
|
(*info->fprintf_func) (info->stream, "%s ",
|
|
float_format_names[0]);
|
|
else
|
|
(*info->fprintf_func) (info->stream, "%s ",
|
|
float_format_names[1]);
|
|
break;
|
|
case 'I':
|
|
/* if no destination completer and not before a completer
|
|
for fcmp, need a space here */
|
|
if (s[1] == '?')
|
|
fputs_filtered
|
|
(float_format_names[GET_FIELD (insn, 20, 20)], info);
|
|
else
|
|
(*info->fprintf_func)
|
|
(info->stream, "%s ",
|
|
float_format_names[GET_FIELD (insn, 20, 20)]);
|
|
break;
|
|
|
|
case 'J':
|
|
fput_const (extract_14 (insn), info);
|
|
break;
|
|
|
|
case '#':
|
|
{
|
|
int sign = GET_FIELD (insn, 31, 31);
|
|
int imm10 = GET_FIELD (insn, 18, 27);
|
|
int disp;
|
|
|
|
if (sign)
|
|
disp = (-1 << 10) | imm10;
|
|
else
|
|
disp = imm10;
|
|
|
|
disp <<= 3;
|
|
fput_const (disp, info);
|
|
break;
|
|
}
|
|
case 'K':
|
|
case 'd':
|
|
{
|
|
int sign = GET_FIELD (insn, 31, 31);
|
|
int imm11 = GET_FIELD (insn, 18, 28);
|
|
int disp;
|
|
|
|
if (sign)
|
|
disp = (-1 << 11) | imm11;
|
|
else
|
|
disp = imm11;
|
|
|
|
disp <<= 2;
|
|
fput_const (disp, info);
|
|
break;
|
|
}
|
|
|
|
case '>':
|
|
case 'y':
|
|
{
|
|
/* 16-bit long disp., PA2.0 wide only. */
|
|
int disp = extract_16 (insn);
|
|
disp &= ~3;
|
|
fput_const (disp, info);
|
|
break;
|
|
}
|
|
|
|
case '&':
|
|
{
|
|
/* 16-bit long disp., PA2.0 wide only. */
|
|
int disp = extract_16 (insn);
|
|
disp &= ~7;
|
|
fput_const (disp, info);
|
|
break;
|
|
}
|
|
|
|
case '_':
|
|
break; /* Dealt with by '{' */
|
|
|
|
case '{':
|
|
{
|
|
int sub = GET_FIELD (insn, 14, 16);
|
|
int df = GET_FIELD (insn, 17, 18);
|
|
int sf = GET_FIELD (insn, 19, 20);
|
|
const char * const * source = float_format_names;
|
|
const char * const * dest = float_format_names;
|
|
char *t = "";
|
|
if (sub == 4)
|
|
{
|
|
fputs_filtered (",UND ", info);
|
|
break;
|
|
}
|
|
if ((sub & 3) == 3)
|
|
t = ",t";
|
|
if ((sub & 3) == 1)
|
|
source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
|
|
if (sub & 2)
|
|
dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
|
|
|
|
(*info->fprintf_func) (info->stream, "%s%s%s ",
|
|
t, source[sf], dest[df]);
|
|
break;
|
|
}
|
|
|
|
case 'm':
|
|
{
|
|
int y = GET_FIELD (insn, 16, 18);
|
|
|
|
if (y != 1)
|
|
fput_const ((y ^ 1) - 1, info);
|
|
}
|
|
break;
|
|
|
|
case 'h':
|
|
{
|
|
int cbit;
|
|
|
|
cbit = GET_FIELD (insn, 16, 18);
|
|
|
|
if (cbit > 0)
|
|
(*info->fprintf_func) (info->stream, ",%d", cbit - 1);
|
|
break;
|
|
}
|
|
|
|
case '=':
|
|
{
|
|
int cond = GET_FIELD (insn, 27, 31);
|
|
|
|
if (cond == 0)
|
|
fputs_filtered (" ", info);
|
|
else if (cond == 1)
|
|
fputs_filtered ("acc ", info);
|
|
else if (cond == 2)
|
|
fputs_filtered ("rej ", info);
|
|
else if (cond == 5)
|
|
fputs_filtered ("acc8 ", info);
|
|
else if (cond == 6)
|
|
fputs_filtered ("rej8 ", info);
|
|
else if (cond == 9)
|
|
fputs_filtered ("acc6 ", info);
|
|
else if (cond == 13)
|
|
fputs_filtered ("acc4 ", info);
|
|
else if (cond == 17)
|
|
fputs_filtered ("acc2 ", info);
|
|
break;
|
|
}
|
|
|
|
case 'X':
|
|
(*info->print_address_func)
|
|
(memaddr + 8 + extract_22 (insn), info);
|
|
break;
|
|
case 'L':
|
|
fputs_filtered (",%r2", info);
|
|
break;
|
|
default:
|
|
(*info->fprintf_func) (info->stream, "%c", *s);
|
|
break;
|
|
}
|
|
}
|
|
return sizeof(insn);
|
|
}
|
|
}
|
|
(*info->fprintf_func) (info->stream, "#%8x", insn);
|
|
return sizeof(insn);
|
|
}
|