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* mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode fields (i.e., add and move commas) so that they more closely match the MIPS ISA documentation opcode partitioning. |
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.. | ||
acconfig.h | ||
ChangeLog | ||
config.in | ||
configure | ||
configure.in | ||
dv-tx3904cpu.c | ||
dv-tx3904irc.c | ||
dv-tx3904sio.c | ||
dv-tx3904tmr.c | ||
interp.c | ||
m16.dc | ||
m16.igen | ||
m16run.c | ||
Makefile.in | ||
mips.dc | ||
mips.igen | ||
sim-main.c | ||
sim-main.h | ||
tconfig.in | ||
tx.igen | ||
vr.igen |