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d306ce58b4
2014-11-28 Sandra Loosemore <sandra@codesourcery.com> include/opcode/ * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. (NIOS2_INSN_OPTARG): Renumber. opcodes/ * nios2-opc.c (nios2_r1_opcodes): Remove deleted attributes from descriptors. gas/ * config/tc-nios2.c (can_evaluate_expr, get_expr_value): Delete. (output_addi, output_andi, output_ori, output_xori): Delete. (md_assemble): Remove calls to deleted functions. gas/testsuite/ * gas/nios2/nios2.exp: Make "movi" a list test. * gas/nios2/movi.s: Adjust comments, add another case. * gas/nios2/movi.l: New. * gas/nios2/movi.d: Delete.
408 lines
17 KiB
C
408 lines
17 KiB
C
/* Altera Nios II opcode list.
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Copyright (C) 2012-2014 Free Software Foundation, Inc.
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Contributed by Nigel Gray (ngray@altera.com).
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Contributed by Mentor Graphics, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "opcode/nios2.h"
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/* Register string table */
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const struct nios2_reg nios2_builtin_regs[] = {
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/* Standard register names. */
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{"zero", 0, REG_NORMAL},
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{"at", 1, REG_NORMAL}, /* assembler temporary */
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{"r2", 2, REG_NORMAL},
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{"r3", 3, REG_NORMAL},
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{"r4", 4, REG_NORMAL},
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{"r5", 5, REG_NORMAL},
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{"r6", 6, REG_NORMAL},
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{"r7", 7, REG_NORMAL},
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{"r8", 8, REG_NORMAL},
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{"r9", 9, REG_NORMAL},
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{"r10", 10, REG_NORMAL},
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{"r11", 11, REG_NORMAL},
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{"r12", 12, REG_NORMAL},
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{"r13", 13, REG_NORMAL},
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{"r14", 14, REG_NORMAL},
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{"r15", 15, REG_NORMAL},
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{"r16", 16, REG_NORMAL},
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{"r17", 17, REG_NORMAL},
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{"r18", 18, REG_NORMAL},
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{"r19", 19, REG_NORMAL},
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{"r20", 20, REG_NORMAL},
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{"r21", 21, REG_NORMAL},
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{"r22", 22, REG_NORMAL},
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{"r23", 23, REG_NORMAL},
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{"et", 24, REG_NORMAL},
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{"bt", 25, REG_NORMAL},
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{"gp", 26, REG_NORMAL}, /* global pointer */
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{"sp", 27, REG_NORMAL}, /* stack pointer */
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{"fp", 28, REG_NORMAL}, /* frame pointer */
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{"ea", 29, REG_NORMAL}, /* exception return address */
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{"sstatus", 30, REG_NORMAL}, /* saved processor status */
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{"ra", 31, REG_NORMAL}, /* return address */
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/* Alternative names for special registers. */
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{"r0", 0, REG_NORMAL},
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{"r1", 1, REG_NORMAL},
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{"r24", 24, REG_NORMAL},
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{"r25", 25, REG_NORMAL},
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{"r26", 26, REG_NORMAL},
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{"r27", 27, REG_NORMAL},
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{"r28", 28, REG_NORMAL},
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{"r29", 29, REG_NORMAL},
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{"r30", 30, REG_NORMAL},
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{"ba", 30, REG_NORMAL}, /* breakpoint return address */
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{"r31", 31, REG_NORMAL},
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/* Control register names. */
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{"status", 0, REG_CONTROL},
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{"estatus", 1, REG_CONTROL},
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{"bstatus", 2, REG_CONTROL},
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{"ienable", 3, REG_CONTROL},
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{"ipending", 4, REG_CONTROL},
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{"cpuid", 5, REG_CONTROL},
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{"ctl6", 6, REG_CONTROL},
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{"exception", 7, REG_CONTROL},
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{"pteaddr", 8, REG_CONTROL},
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{"tlbacc", 9, REG_CONTROL},
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{"tlbmisc", 10, REG_CONTROL},
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{"eccinj", 11, REG_CONTROL},
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{"badaddr", 12, REG_CONTROL},
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{"config", 13, REG_CONTROL},
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{"mpubase", 14, REG_CONTROL},
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{"mpuacc", 15, REG_CONTROL},
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{"ctl16", 16, REG_CONTROL},
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{"ctl17", 17, REG_CONTROL},
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{"ctl18", 18, REG_CONTROL},
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{"ctl19", 19, REG_CONTROL},
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{"ctl20", 20, REG_CONTROL},
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{"ctl21", 21, REG_CONTROL},
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{"ctl22", 22, REG_CONTROL},
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{"ctl23", 23, REG_CONTROL},
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{"ctl24", 24, REG_CONTROL},
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{"ctl25", 25, REG_CONTROL},
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{"ctl26", 26, REG_CONTROL},
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{"ctl27", 27, REG_CONTROL},
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{"ctl28", 28, REG_CONTROL},
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{"ctl29", 29, REG_CONTROL},
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{"ctl30", 30, REG_CONTROL},
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{"ctl31", 31, REG_CONTROL},
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/* Alternative names for special control registers. */
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{"ctl0", 0, REG_CONTROL},
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{"ctl1", 1, REG_CONTROL},
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{"ctl2", 2, REG_CONTROL},
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{"ctl3", 3, REG_CONTROL},
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{"ctl4", 4, REG_CONTROL},
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{"ctl5", 5, REG_CONTROL},
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{"ctl7", 7, REG_CONTROL},
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{"ctl8", 8, REG_CONTROL},
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{"ctl9", 9, REG_CONTROL},
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{"ctl10", 10, REG_CONTROL},
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{"ctl11", 11, REG_CONTROL},
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{"ctl12", 12, REG_CONTROL},
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{"ctl13", 13, REG_CONTROL},
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{"ctl14", 14, REG_CONTROL},
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{"ctl15", 15, REG_CONTROL},
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/* Coprocessor register names. */
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{"c0", 0, REG_COPROCESSOR},
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{"c1", 1, REG_COPROCESSOR},
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{"c2", 2, REG_COPROCESSOR},
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{"c3", 3, REG_COPROCESSOR},
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{"c4", 4, REG_COPROCESSOR},
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{"c5", 5, REG_COPROCESSOR},
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{"c6", 6, REG_COPROCESSOR},
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{"c7", 7, REG_COPROCESSOR},
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{"c8", 8, REG_COPROCESSOR},
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{"c9", 9, REG_COPROCESSOR},
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{"c10", 10, REG_COPROCESSOR},
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{"c11", 11, REG_COPROCESSOR},
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{"c12", 12, REG_COPROCESSOR},
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{"c13", 13, REG_COPROCESSOR},
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{"c14", 14, REG_COPROCESSOR},
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{"c15", 15, REG_COPROCESSOR},
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{"c16", 16, REG_COPROCESSOR},
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{"c17", 17, REG_COPROCESSOR},
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{"c18", 18, REG_COPROCESSOR},
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{"c19", 19, REG_COPROCESSOR},
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{"c20", 20, REG_COPROCESSOR},
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{"c21", 21, REG_COPROCESSOR},
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{"c22", 22, REG_COPROCESSOR},
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{"c23", 23, REG_COPROCESSOR},
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{"c24", 24, REG_COPROCESSOR},
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{"c25", 25, REG_COPROCESSOR},
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{"c26", 26, REG_COPROCESSOR},
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{"c27", 27, REG_COPROCESSOR},
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{"c28", 28, REG_COPROCESSOR},
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{"c29", 29, REG_COPROCESSOR},
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{"c30", 30, REG_COPROCESSOR},
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{"c31", 31, REG_COPROCESSOR},
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};
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#define NIOS2_NUM_REGS \
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((sizeof nios2_builtin_regs) / (sizeof (nios2_builtin_regs[0])))
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const int nios2_num_builtin_regs = NIOS2_NUM_REGS;
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/* This is not const in order to allow for dynamic extensions to the
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built-in instruction set. */
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struct nios2_reg *nios2_regs = (struct nios2_reg *) nios2_builtin_regs;
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int nios2_num_regs = NIOS2_NUM_REGS;
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#undef NIOS2_NUM_REGS
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/* This is the opcode table used by the Nios II GNU as, disassembler
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and GDB. */
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const struct nios2_opcode nios2_r1_opcodes[] =
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{
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/* { name, args, args_test, num_args, size, format,
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match, mask, pinfo, overflow } */
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{"add", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_ADD, MASK_R1_ADD, 0, no_overflow},
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{"addi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_ADDI, MASK_R1_ADDI, 0, signed_immed16_overflow},
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{"and", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_AND, MASK_R1_AND, 0, no_overflow},
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{"andhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_ANDHI, MASK_R1_ANDHI, 0, unsigned_immed16_overflow},
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{"andi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_ANDI, MASK_R1_ANDI, 0, unsigned_immed16_overflow},
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{"beq", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BEQ, MASK_R1_BEQ, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bge", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BGE, MASK_R1_BGE, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bgeu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BGEU, MASK_R1_BGEU, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bgt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BGT, MASK_R1_BGT,
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NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bgtu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BGTU, MASK_R1_BGTU,
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NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"ble", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BLE, MASK_R1_BLE,
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NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bleu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BLEU, MASK_R1_BLEU,
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NIOS2_INSN_MACRO|NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"blt", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BLT, MASK_R1_BLT, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bltu", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BLTU, MASK_R1_BLTU, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"bne", "s,t,o", "s,t,o,E", 3, 4, iw_i_type,
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MATCH_R1_BNE, MASK_R1_BNE, NIOS2_INSN_CBRANCH, branch_target_overflow},
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{"br", "o", "o,E", 1, 4, iw_i_type,
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MATCH_R1_BR, MASK_R1_BR, NIOS2_INSN_UBRANCH, branch_target_overflow},
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{"break", "j", "j,E", 1, 4, iw_r_type,
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MATCH_R1_BREAK, MASK_R1_BREAK, NIOS2_INSN_OPTARG, no_overflow},
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{"bret", "", "E", 0, 4, iw_r_type,
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MATCH_R1_BRET, MASK_R1_BRET, 0, no_overflow},
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{"call", "m", "m,E", 1, 4, iw_j_type,
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MATCH_R1_CALL, MASK_R1_CALL, NIOS2_INSN_CALL, call_target_overflow},
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{"callr", "s", "s,E", 1, 4, iw_r_type,
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MATCH_R1_CALLR, MASK_R1_CALLR, 0, no_overflow},
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{"cmpeq", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPEQ, MASK_R1_CMPEQ, 0, no_overflow},
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{"cmpeqi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPEQI, MASK_R1_CMPEQI, 0, signed_immed16_overflow},
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{"cmpge", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPGE, MASK_R1_CMPGE, 0, no_overflow},
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{"cmpgei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPGEI, MASK_R1_CMPGEI, 0, signed_immed16_overflow},
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{"cmpgeu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPGEU, MASK_R1_CMPGEU, 0, no_overflow},
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{"cmpgeui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_CMPGEUI, MASK_R1_CMPGEUI, 0, unsigned_immed16_overflow},
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{"cmpgt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPGT, MASK_R1_CMPGT, NIOS2_INSN_MACRO, no_overflow},
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{"cmpgti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPGTI, MASK_R1_CMPGTI, NIOS2_INSN_MACRO, signed_immed16_overflow},
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{"cmpgtu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPGTU, MASK_R1_CMPGTU, NIOS2_INSN_MACRO, no_overflow},
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{"cmpgtui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_CMPGTUI, MASK_R1_CMPGTUI,
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NIOS2_INSN_MACRO, unsigned_immed16_overflow},
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{"cmple", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPLE, MASK_R1_CMPLE, NIOS2_INSN_MACRO, no_overflow},
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{"cmplei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPLEI, MASK_R1_CMPLEI, NIOS2_INSN_MACRO, signed_immed16_overflow},
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{"cmpleu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPLEU, MASK_R1_CMPLEU, NIOS2_INSN_MACRO, no_overflow},
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{"cmpleui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_CMPLEUI, MASK_R1_CMPLEUI,
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NIOS2_INSN_MACRO, unsigned_immed16_overflow},
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{"cmplt", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPLT, MASK_R1_CMPLT, 0, no_overflow},
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{"cmplti", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPLTI, MASK_R1_CMPLTI, 0, signed_immed16_overflow},
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{"cmpltu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPLTU, MASK_R1_CMPLTU, 0, no_overflow},
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{"cmpltui", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
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MATCH_R1_CMPLTUI, MASK_R1_CMPLTUI, 0, unsigned_immed16_overflow},
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{"cmpne", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_CMPNE, MASK_R1_CMPNE, 0, no_overflow},
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{"cmpnei", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
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MATCH_R1_CMPNEI, MASK_R1_CMPNEI, 0, signed_immed16_overflow},
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{"custom", "l,d,s,t", "l,d,s,t,E", 4, 4, iw_custom_type,
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MATCH_R1_CUSTOM, MASK_R1_CUSTOM, 0, custom_opcode_overflow},
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{"div", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_DIV, MASK_R1_DIV, 0, no_overflow},
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{"divu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
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MATCH_R1_DIVU, MASK_R1_DIVU, 0, no_overflow},
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{"eret", "", "E", 0, 4, iw_r_type,
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MATCH_R1_ERET, MASK_R1_ERET, 0, no_overflow},
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{"flushd", "i(s)", "i(s),E", 2, 4, iw_i_type,
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MATCH_R1_FLUSHD, MASK_R1_FLUSHD, 0, address_offset_overflow},
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{"flushda", "i(s)", "i(s),E", 2, 4, iw_i_type,
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MATCH_R1_FLUSHDA, MASK_R1_FLUSHDA, 0, address_offset_overflow},
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{"flushi", "s", "s,E", 1, 4, iw_r_type,
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MATCH_R1_FLUSHI, MASK_R1_FLUSHI, 0, no_overflow},
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{"flushp", "", "E", 0, 4, iw_r_type,
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MATCH_R1_FLUSHP, MASK_R1_FLUSHP, 0, no_overflow},
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{"initd", "i(s)", "i(s),E", 2, 4, iw_i_type,
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MATCH_R1_INITD, MASK_R1_INITD, 0, address_offset_overflow},
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{"initda", "i(s)", "i(s),E", 2, 4, iw_i_type,
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MATCH_R1_INITDA, MASK_R1_INITDA, 0, address_offset_overflow},
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{"initi", "s", "s,E", 1, 4, iw_r_type,
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MATCH_R1_INITI, MASK_R1_INITI, 0, no_overflow},
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{"jmp", "s", "s,E", 1, 4, iw_r_type,
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MATCH_R1_JMP, MASK_R1_JMP, 0, no_overflow},
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{"jmpi", "m", "m,E", 1, 4, iw_j_type,
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MATCH_R1_JMPI, MASK_R1_JMPI, 0, call_target_overflow},
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{"ldb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDB, MASK_R1_LDB, 0, address_offset_overflow},
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{"ldbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDBIO, MASK_R1_LDBIO, 0, address_offset_overflow},
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{"ldbu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDBU, MASK_R1_LDBU, 0, address_offset_overflow},
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{"ldbuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDBUIO, MASK_R1_LDBUIO, 0, address_offset_overflow},
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{"ldh", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDH, MASK_R1_LDH, 0, address_offset_overflow},
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{"ldhio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDHIO, MASK_R1_LDHIO, 0, address_offset_overflow},
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{"ldhu", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDHU, MASK_R1_LDHU, 0, address_offset_overflow},
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|
{"ldhuio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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MATCH_R1_LDHUIO, MASK_R1_LDHUIO, 0, address_offset_overflow},
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|
{"ldw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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|
MATCH_R1_LDW, MASK_R1_LDW, 0, address_offset_overflow},
|
|
{"ldwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
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|
MATCH_R1_LDWIO, MASK_R1_LDWIO, 0, address_offset_overflow},
|
|
{"mov", "d,s", "d,s,E", 2, 4, iw_r_type,
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|
MATCH_R1_MOV, MASK_R1_MOV, NIOS2_INSN_MACRO_MOV, no_overflow},
|
|
{"movhi", "t,u", "t,u,E", 2, 4, iw_i_type,
|
|
MATCH_R1_MOVHI, MASK_R1_MOVHI,
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|
NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
|
|
{"movi", "t,i", "t,i,E", 2, 4, iw_i_type,
|
|
MATCH_R1_MOVI, MASK_R1_MOVI, NIOS2_INSN_MACRO_MOVI, signed_immed16_overflow},
|
|
{"movia", "t,o", "t,o,E", 2, 4, iw_i_type,
|
|
MATCH_R1_ORHI, MASK_R1_ORHI, NIOS2_INSN_MACRO_MOVIA, no_overflow},
|
|
{"movui", "t,u", "t,u,E", 2, 4, iw_i_type,
|
|
MATCH_R1_MOVUI, MASK_R1_MOVUI,
|
|
NIOS2_INSN_MACRO_MOVI, unsigned_immed16_overflow},
|
|
{"mul", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_MUL, MASK_R1_MUL, 0, no_overflow},
|
|
{"muli", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
|
|
MATCH_R1_MULI, MASK_R1_MULI, 0, signed_immed16_overflow},
|
|
{"mulxss", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_MULXSS, MASK_R1_MULXSS, 0, no_overflow},
|
|
{"mulxsu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_MULXSU, MASK_R1_MULXSU, 0, no_overflow},
|
|
{"mulxuu", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_MULXUU, MASK_R1_MULXUU, 0, no_overflow},
|
|
{"nextpc", "d", "d,E", 1, 4, iw_r_type,
|
|
MATCH_R1_NEXTPC, MASK_R1_NEXTPC, 0, no_overflow},
|
|
{"nop", "", "E", 0, 4, iw_r_type,
|
|
MATCH_R1_NOP, MASK_R1_NOP, NIOS2_INSN_MACRO_MOV, no_overflow},
|
|
{"nor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_NOR, MASK_R1_NOR, 0, no_overflow},
|
|
{"or", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_OR, MASK_R1_OR, 0, no_overflow},
|
|
{"orhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
|
|
MATCH_R1_ORHI, MASK_R1_ORHI, 0, unsigned_immed16_overflow},
|
|
{"ori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
|
|
MATCH_R1_ORI, MASK_R1_ORI, 0, unsigned_immed16_overflow},
|
|
{"rdctl", "d,c", "d,c,E", 2, 4, iw_r_type,
|
|
MATCH_R1_RDCTL, MASK_R1_RDCTL, 0, no_overflow},
|
|
{"rdprs", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
|
|
MATCH_R1_RDPRS, MASK_R1_RDPRS, 0, signed_immed16_overflow},
|
|
{"ret", "", "E", 0, 4, iw_r_type,
|
|
MATCH_R1_RET, MASK_R1_RET, 0, no_overflow},
|
|
{"rol", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_ROL, MASK_R1_ROL, 0, no_overflow},
|
|
{"roli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
|
|
MATCH_R1_ROLI, MASK_R1_ROLI, 0, unsigned_immed5_overflow},
|
|
{"ror", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_ROR, MASK_R1_ROR, 0, no_overflow},
|
|
{"sll", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SLL, MASK_R1_SLL, 0, no_overflow},
|
|
{"slli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SLLI, MASK_R1_SLLI, 0, unsigned_immed5_overflow},
|
|
{"sra", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SRA, MASK_R1_SRA, 0, no_overflow},
|
|
{"srai", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SRAI, MASK_R1_SRAI, 0, unsigned_immed5_overflow},
|
|
{"srl", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SRL, MASK_R1_SRL, 0, no_overflow},
|
|
{"srli", "d,s,j", "d,s,j,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SRLI, MASK_R1_SRLI, 0, unsigned_immed5_overflow},
|
|
{"stb", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STB, MASK_R1_STB, 0, address_offset_overflow},
|
|
{"stbio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STBIO, MASK_R1_STBIO, 0, address_offset_overflow},
|
|
{"sth", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STH, MASK_R1_STH, 0, address_offset_overflow},
|
|
{"sthio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STHIO, MASK_R1_STHIO, 0, address_offset_overflow},
|
|
{"stw", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STW, MASK_R1_STW, 0, address_offset_overflow},
|
|
{"stwio", "t,i(s)", "t,i(s),E", 3, 4, iw_i_type,
|
|
MATCH_R1_STWIO, MASK_R1_STWIO, 0, address_offset_overflow},
|
|
{"sub", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_SUB, MASK_R1_SUB, 0, no_overflow},
|
|
{"subi", "t,s,i", "t,s,i,E", 3, 4, iw_i_type,
|
|
MATCH_R1_SUBI, MASK_R1_SUBI, NIOS2_INSN_MACRO, signed_immed16_overflow},
|
|
{"sync", "", "E", 0, 4, iw_r_type,
|
|
MATCH_R1_SYNC, MASK_R1_SYNC, 0, no_overflow},
|
|
{"trap", "j", "j,E", 1, 4, iw_r_type,
|
|
MATCH_R1_TRAP, MASK_R1_TRAP, NIOS2_INSN_OPTARG, no_overflow},
|
|
{"wrctl", "c,s", "c,s,E", 2, 4, iw_r_type,
|
|
MATCH_R1_WRCTL, MASK_R1_WRCTL, 0, no_overflow},
|
|
{"wrprs", "d,s", "d,s,E", 2, 4, iw_r_type,
|
|
MATCH_R1_WRPRS, MASK_R1_WRPRS, 0, no_overflow},
|
|
{"xor", "d,s,t", "d,s,t,E", 3, 4, iw_r_type,
|
|
MATCH_R1_XOR, MASK_R1_XOR, 0, no_overflow},
|
|
{"xorhi", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
|
|
MATCH_R1_XORHI, MASK_R1_XORHI, 0, unsigned_immed16_overflow},
|
|
{"xori", "t,s,u", "t,s,u,E", 3, 4, iw_i_type,
|
|
MATCH_R1_XORI, MASK_R1_XORI, 0, unsigned_immed16_overflow}
|
|
};
|
|
|
|
#define NIOS2_NUM_OPCODES \
|
|
((sizeof nios2_r1_opcodes) / (sizeof (nios2_r1_opcodes[0])))
|
|
const int nios2_num_r1_opcodes = NIOS2_NUM_OPCODES;
|
|
|
|
struct nios2_opcode *nios2_opcodes = (struct nios2_opcode *) nios2_r1_opcodes;
|
|
int nios2_num_opcodes = NIOS2_NUM_OPCODES;
|
|
#undef NIOS2_NUM_OPCODES
|