mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-02 23:04:09 +08:00
0820c9f5fc
gas/ChangeLog:
* config/tc-i386.c (build_modrm_byte): Dropped the use of
SWAP_SOURCES to encode the vvvv register.
opcodes/ChangeLog:
* i386-opc.h (SWAP_SOURCES): Dropped.
(NO_DEFAULT_MASK): Adjusted the value.
(ADDR_PREFIX_OP_REG): Ditto.
(DISTINCT_DEST): Ditto.
(IMPLICIT_STACK_OP): Ditto.
(VexVVVV_SRC2): New.
* i386-opc.tbl: Dropped SwapSources and replaced its VexVVVV
with Src1VVVV.
* i386-tbl.h: Regenerated.
1060 lines
30 KiB
C
1060 lines
30 KiB
C
/* Declarations for Intel 80386 opcode table
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Copyright (C) 2007-2024 Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
||
the Free Software Foundation; either version 3, or (at your option)
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||
any later version.
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||
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||
It is distributed in the hope that it will be useful, but WITHOUT
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||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||
License for more details.
|
||
|
||
You should have received a copy of the GNU General Public License
|
||
along with GAS; see the file COPYING. If not, write to the Free
|
||
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "opcode/i386.h"
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#include <limits.h>
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#ifndef CHAR_BIT
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#define CHAR_BIT 8
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#endif
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/* Position of cpu flags bitfiled. */
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enum i386_cpu
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{
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/* i186 or better required */
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Cpu186 = 0,
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/* i286 or better required */
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Cpu286,
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/* i386 or better required */
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Cpu386,
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/* i486 or better required */
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Cpu486,
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/* i585 or better required */
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Cpu586,
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/* i686 or better required */
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Cpu686,
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/* CMOV Instruction support required */
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CpuCMOV,
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/* FXSR Instruction support required */
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CpuFXSR,
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/* CLFLUSH Instruction support required */
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CpuClflush,
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/* NOP Instruction support required */
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CpuNop,
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/* SYSCALL Instructions support required */
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CpuSYSCALL,
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/* Floating point support required */
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Cpu8087,
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/* i686 and floating point support required */
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Cpu687,
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/* SSE3 and floating point support required */
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CpuFISTTP,
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/* MMX support required */
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CpuMMX,
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/* SSE support required */
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CpuSSE,
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/* SSE2 support required */
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CpuSSE2,
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/* SSE3 support required */
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CpuSSE3,
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/* VIA PadLock required */
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CpuPadLock,
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/* AMD Secure Virtual Machine Ext-s required */
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CpuSVME,
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/* VMX Instructions required */
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CpuVMX,
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/* SMX Instructions required */
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CpuSMX,
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/* SSSE3 support required */
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CpuSSSE3,
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/* SSE4a support required */
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CpuSSE4a,
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/* LZCNT support required */
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CpuLZCNT,
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/* POPCNT support required */
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CpuPOPCNT,
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/* MONITOR support required */
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CpuMONITOR,
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/* SSE4.1 support required */
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CpuSSE4_1,
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/* SSE4.2 support required */
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CpuSSE4_2,
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/* AVX2 support required */
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CpuAVX2,
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/* Intel AVX-512 Conflict Detection Instructions support required */
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CpuAVX512CD,
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/* Intel AVX-512 Exponential and Reciprocal Instructions support
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required */
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CpuAVX512ER,
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/* Intel AVX-512 Prefetch Instructions support required */
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CpuAVX512PF,
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/* Intel AVX-512 DQ Instructions support required. */
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CpuAVX512DQ,
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/* Intel AVX-512 BW Instructions support required. */
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CpuAVX512BW,
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/* Intel IAMCU support required */
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CpuIAMCU,
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/* Xsave/xrstor New Instructions support required */
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CpuXsave,
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/* Xsaveopt New Instructions support required */
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CpuXsaveopt,
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/* AES support required */
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CpuAES,
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/* PCLMULQDQ support required */
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CpuPCLMULQDQ,
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/* FMA support required */
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CpuFMA,
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/* FMA4 support required */
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CpuFMA4,
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/* XOP support required */
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CpuXOP,
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/* LWP support required */
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CpuLWP,
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/* BMI support required */
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CpuBMI,
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/* TBM support required */
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CpuTBM,
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/* MOVBE Instruction support required */
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CpuMovbe,
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/* CMPXCHG16B instruction support required. */
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CpuCX16,
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/* LAHF/SAHF instruction support required (in 64-bit mode). */
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CpuLAHF_SAHF,
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/* EPT Instructions required */
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CpuEPT,
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/* RDTSCP Instruction support required */
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CpuRdtscp,
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/* FSGSBASE Instructions required */
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CpuFSGSBase,
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/* RDRND Instructions required */
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CpuRdRnd,
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/* F16C Instructions required */
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CpuF16C,
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/* Intel BMI2 support required */
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CpuBMI2,
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/* RTM support required */
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CpuRTM,
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/* INVPCID Instructions required */
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CpuINVPCID,
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/* VMFUNC Instruction required */
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CpuVMFUNC,
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/* Intel MPX Instructions required */
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CpuMPX,
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/* RDRSEED instruction required. */
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CpuRDSEED,
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/* Multi-presisionn add-carry instructions are required. */
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CpuADX,
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/* Supports prefetchw and prefetch instructions. */
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CpuPRFCHW,
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/* SMAP instructions required. */
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CpuSMAP,
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/* SHA instructions required. */
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CpuSHA,
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/* SHA512 instructions required. */
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CpuSHA512,
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/* SM3 instructions required. */
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CpuSM3,
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/* SM4 instructions required. */
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CpuSM4,
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/* CLFLUSHOPT instruction required */
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CpuClflushOpt,
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/* XSAVES/XRSTORS instruction required */
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CpuXSAVES,
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/* XSAVEC instruction required */
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CpuXSAVEC,
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/* PREFETCHWT1 instruction required */
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CpuPREFETCHWT1,
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/* SE1 instruction required */
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CpuSE1,
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/* CLWB instruction required */
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CpuCLWB,
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/* Intel AVX-512 IFMA Instructions support required. */
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CpuAVX512IFMA,
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/* Intel AVX-512 VBMI Instructions support required. */
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CpuAVX512VBMI,
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/* Intel AVX-512 4FMAPS Instructions support required. */
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CpuAVX512_4FMAPS,
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/* Intel AVX-512 4VNNIW Instructions support required. */
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CpuAVX512_4VNNIW,
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/* Intel AVX-512 VPOPCNTDQ Instructions support required. */
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CpuAVX512_VPOPCNTDQ,
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/* Intel AVX-512 VBMI2 Instructions support required. */
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CpuAVX512_VBMI2,
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/* Intel AVX-512 VNNI Instructions support required. */
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CpuAVX512_VNNI,
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/* Intel AVX-512 BITALG Instructions support required. */
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CpuAVX512_BITALG,
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/* Intel AVX-512 BF16 Instructions support required. */
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CpuAVX512_BF16,
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/* Intel AVX-512 VP2INTERSECT Instructions support required. */
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CpuAVX512_VP2INTERSECT,
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/* TDX Instructions support required. */
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CpuTDX,
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/* Intel AVX VNNI Instructions support required. */
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CpuAVX_VNNI,
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/* Intel AVX-512 FP16 Instructions support required. */
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CpuAVX512_FP16,
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/* PREFETCHI instruction required */
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CpuPREFETCHI,
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/* Intel AVX IFMA Instructions support required. */
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CpuAVX_IFMA,
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/* Intel AVX VNNI-INT8 Instructions support required. */
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CpuAVX_VNNI_INT8,
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/* Intel AVX VNNI-INT16 Instructions support required. */
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CpuAVX_VNNI_INT16,
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/* Intel CMPccXADD instructions support required. */
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CpuCMPCCXADD,
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/* Intel WRMSRNS Instructions support required */
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CpuWRMSRNS,
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/* Intel MSRLIST Instructions support required. */
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CpuMSRLIST,
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/* Intel AVX NE CONVERT Instructions support required. */
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CpuAVX_NE_CONVERT,
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/* Intel RAO INT Instructions support required. */
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CpuRAO_INT,
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/* fred instruction required */
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CpuFRED,
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/* lkgs instruction required */
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CpuLKGS,
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/* Intel USER_MSR Instruction support required. */
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CpuUSER_MSR,
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/* mwaitx instruction required */
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CpuMWAITX,
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/* Clzero instruction required */
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CpuCLZERO,
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/* OSPKE instruction required */
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CpuOSPKE,
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/* RDPID instruction required */
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CpuRDPID,
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/* PTWRITE instruction required */
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CpuPTWRITE,
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/* CET instructions support required */
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CpuIBT,
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CpuSHSTK,
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/* AMX-INT8 instructions required */
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CpuAMX_INT8,
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/* AMX-BF16 instructions required */
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CpuAMX_BF16,
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/* AMX-FP16 instructions required */
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CpuAMX_FP16,
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/* AMX-COMPLEX instructions required. */
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CpuAMX_COMPLEX,
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/* AMX-TILE instructions required */
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CpuAMX_TILE,
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/* GFNI instructions required */
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CpuGFNI,
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/* VAES instructions required */
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CpuVAES,
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/* VPCLMULQDQ instructions required */
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CpuVPCLMULQDQ,
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/* WBNOINVD instructions required */
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CpuWBNOINVD,
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/* PCONFIG instructions required */
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CpuPCONFIG,
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/* PBNDKB instructions required. */
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CpuPBNDKB,
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/* WAITPKG instructions required */
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CpuWAITPKG,
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/* UINTR instructions required */
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CpuUINTR,
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/* CLDEMOTE instruction required */
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CpuCLDEMOTE,
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/* MOVDIRI instruction support required */
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CpuMOVDIRI,
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/* MOVDIRR64B instruction required */
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CpuMOVDIR64B,
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/* ENQCMD instruction required */
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CpuENQCMD,
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/* SERIALIZE instruction required */
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CpuSERIALIZE,
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/* RDPRU instruction required */
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CpuRDPRU,
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/* MCOMMIT instruction required */
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CpuMCOMMIT,
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/* SEV-ES instruction(s) required */
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CpuSEV_ES,
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/* TSXLDTRK instruction required */
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CpuTSXLDTRK,
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/* KL instruction support required */
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CpuKL,
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/* WideKL instruction support required */
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CpuWideKL,
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/* HRESET instruction required */
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CpuHRESET,
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/* INVLPGB instructions required */
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CpuINVLPGB,
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/* TLBSYNC instructions required */
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CpuTLBSYNC,
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/* SNP instructions required */
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CpuSNP,
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/* RMPQUERY instruction required */
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CpuRMPQUERY,
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/* NOTE: These items, which can be combined with other ISA flags above, need
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to remain second to last and in sync with CPU_FLAGS_COMMON. */
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/* i287 support required */
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Cpu287,
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CpuAttrEnums = Cpu287,
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/* i387 support required */
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Cpu387,
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/* 3dnow! support required */
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Cpu3dnow,
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/* 3dnow! Extensions support required */
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Cpu3dnowA,
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/* 64bit support required */
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Cpu64,
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/* AVX support required */
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CpuAVX,
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/* HLE support required */
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CpuHLE,
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/* Intel AVX-512 Foundation Instructions support required */
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CpuAVX512F,
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/* Intel AVX-512 VL Instructions support required. */
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CpuAVX512VL,
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/* Intel APX_F Instructions support required. */
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CpuAPX_F,
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/* Not supported in the 64bit mode */
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CpuNo64,
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/* NOTE: This item needs to remain last. */
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/* The last bitfield in i386_cpu_flags. */
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CpuMax = CpuNo64
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};
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#define CpuNumOfUints \
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(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
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#define CpuNumOfBits \
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(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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#define CpuIsaBits 8
|
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#define CpuAttrNumOfUints \
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((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1)
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#define CpuAttrNumOfBits \
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(CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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|
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/* If you get a compiler error for zero width of an unused field,
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comment the respective one out. */
|
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#define CpuUnused (CpuMax + 1)
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#define CpuAttrUnused (CpuIsaBits + CpuMax + 1 - CpuAttrEnums)
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|
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#define CPU_FLAGS_COMMON \
|
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unsigned int cpu287:1, \
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cpu387:1, \
|
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cpu3dnow:1, \
|
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cpu3dnowa:1, \
|
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cpu64:1, \
|
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cpuavx:1, \
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cpuhle:1, \
|
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cpuavx512f:1, \
|
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cpuavx512vl:1, \
|
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cpuapx_f:1, \
|
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/* NOTE: This field needs to remain last. */ \
|
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cpuno64:1
|
||
|
||
typedef union i386_cpu_attr
|
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{
|
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struct
|
||
{
|
||
unsigned int isa:CpuIsaBits;
|
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CPU_FLAGS_COMMON;
|
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#ifdef CpuAttrUnused
|
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unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused);
|
||
#endif
|
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} bitfield;
|
||
unsigned int array[CpuAttrNumOfUints];
|
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} i386_cpu_attr;
|
||
|
||
/* We can check if an instruction is available with array instead
|
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of bitfield. */
|
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typedef union i386_cpu_flags
|
||
{
|
||
struct
|
||
{
|
||
unsigned int cpui186:1;
|
||
unsigned int cpui286:1;
|
||
unsigned int cpui386:1;
|
||
unsigned int cpui486:1;
|
||
unsigned int cpui586:1;
|
||
unsigned int cpui686:1;
|
||
unsigned int cpucmov:1;
|
||
unsigned int cpufxsr:1;
|
||
unsigned int cpuclflush:1;
|
||
unsigned int cpunop:1;
|
||
unsigned int cpusyscall:1;
|
||
unsigned int cpu8087:1;
|
||
unsigned int cpu687:1;
|
||
unsigned int cpufisttp:1;
|
||
unsigned int cpummx:1;
|
||
unsigned int cpusse:1;
|
||
unsigned int cpusse2:1;
|
||
unsigned int cpusse3:1;
|
||
unsigned int cpupadlock:1;
|
||
unsigned int cpusvme:1;
|
||
unsigned int cpuvmx:1;
|
||
unsigned int cpusmx:1;
|
||
unsigned int cpussse3:1;
|
||
unsigned int cpusse4a:1;
|
||
unsigned int cpulzcnt:1;
|
||
unsigned int cpupopcnt:1;
|
||
unsigned int cpumonitor:1;
|
||
unsigned int cpusse4_1:1;
|
||
unsigned int cpusse4_2:1;
|
||
unsigned int cpuavx2:1;
|
||
unsigned int cpuavx512cd:1;
|
||
unsigned int cpuavx512er:1;
|
||
unsigned int cpuavx512pf:1;
|
||
unsigned int cpuavx512dq:1;
|
||
unsigned int cpuavx512bw:1;
|
||
unsigned int cpuiamcu:1;
|
||
unsigned int cpuxsave:1;
|
||
unsigned int cpuxsaveopt:1;
|
||
unsigned int cpuaes:1;
|
||
unsigned int cpupclmulqdq:1;
|
||
unsigned int cpufma:1;
|
||
unsigned int cpufma4:1;
|
||
unsigned int cpuxop:1;
|
||
unsigned int cpulwp:1;
|
||
unsigned int cpubmi:1;
|
||
unsigned int cputbm:1;
|
||
unsigned int cpumovbe:1;
|
||
unsigned int cpucx16:1;
|
||
unsigned int cpulahf_sahf:1;
|
||
unsigned int cpuept:1;
|
||
unsigned int cpurdtscp:1;
|
||
unsigned int cpufsgsbase:1;
|
||
unsigned int cpurdrnd:1;
|
||
unsigned int cpuf16c:1;
|
||
unsigned int cpubmi2:1;
|
||
unsigned int cpurtm:1;
|
||
unsigned int cpuinvpcid:1;
|
||
unsigned int cpuvmfunc:1;
|
||
unsigned int cpumpx:1;
|
||
unsigned int cpurdseed:1;
|
||
unsigned int cpuadx:1;
|
||
unsigned int cpuprfchw:1;
|
||
unsigned int cpusmap:1;
|
||
unsigned int cpusha:1;
|
||
unsigned int cpusha512:1;
|
||
unsigned int cpusm3:1;
|
||
unsigned int cpusm4:1;
|
||
unsigned int cpuclflushopt:1;
|
||
unsigned int cpuxsaves:1;
|
||
unsigned int cpuxsavec:1;
|
||
unsigned int cpuprefetchwt1:1;
|
||
unsigned int cpuse1:1;
|
||
unsigned int cpuclwb:1;
|
||
unsigned int cpuavx512ifma:1;
|
||
unsigned int cpuavx512vbmi:1;
|
||
unsigned int cpuavx512_4fmaps:1;
|
||
unsigned int cpuavx512_4vnniw:1;
|
||
unsigned int cpuavx512_vpopcntdq:1;
|
||
unsigned int cpuavx512_vbmi2:1;
|
||
unsigned int cpuavx512_vnni:1;
|
||
unsigned int cpuavx512_bitalg:1;
|
||
unsigned int cpuavx512_bf16:1;
|
||
unsigned int cpuavx512_vp2intersect:1;
|
||
unsigned int cputdx:1;
|
||
unsigned int cpuavx_vnni:1;
|
||
unsigned int cpuavx512_fp16:1;
|
||
unsigned int cpuprefetchi:1;
|
||
unsigned int cpuavx_ifma:1;
|
||
unsigned int cpuavx_vnni_int8:1;
|
||
unsigned int cpuavx_vnni_int16:1;
|
||
unsigned int cpucmpccxadd:1;
|
||
unsigned int cpuwrmsrns:1;
|
||
unsigned int cpumsrlist:1;
|
||
unsigned int cpuavx_ne_convert:1;
|
||
unsigned int cpurao_int:1;
|
||
unsigned int cpufred:1;
|
||
unsigned int cpulkgs:1;
|
||
unsigned int cpuuser_msr:1;
|
||
unsigned int cpumwaitx:1;
|
||
unsigned int cpuclzero:1;
|
||
unsigned int cpuospke:1;
|
||
unsigned int cpurdpid:1;
|
||
unsigned int cpuptwrite:1;
|
||
unsigned int cpuibt:1;
|
||
unsigned int cpushstk:1;
|
||
unsigned int cpuamx_int8:1;
|
||
unsigned int cpuamx_bf16:1;
|
||
unsigned int cpuamx_fp16:1;
|
||
unsigned int cpuamx_complex:1;
|
||
unsigned int cpuamx_tile:1;
|
||
unsigned int cpugfni:1;
|
||
unsigned int cpuvaes:1;
|
||
unsigned int cpuvpclmulqdq:1;
|
||
unsigned int cpuwbnoinvd:1;
|
||
unsigned int cpupconfig:1;
|
||
unsigned int cpupbndkb:1;
|
||
unsigned int cpuwaitpkg:1;
|
||
unsigned int cpuuintr:1;
|
||
unsigned int cpucldemote:1;
|
||
unsigned int cpumovdiri:1;
|
||
unsigned int cpumovdir64b:1;
|
||
unsigned int cpuenqcmd:1;
|
||
unsigned int cpuserialize:1;
|
||
unsigned int cpurdpru:1;
|
||
unsigned int cpumcommit:1;
|
||
unsigned int cpusev_es:1;
|
||
unsigned int cputsxldtrk:1;
|
||
unsigned int cpukl:1;
|
||
unsigned int cpuwidekl:1;
|
||
unsigned int cpuhreset:1;
|
||
unsigned int cpuinvlpgb:1;
|
||
unsigned int cputlbsync:1;
|
||
unsigned int cpusnp:1;
|
||
unsigned int cpurmpquery:1;
|
||
CPU_FLAGS_COMMON;
|
||
#ifdef CpuUnused
|
||
unsigned int unused:(CpuNumOfBits - CpuUnused);
|
||
#endif
|
||
} bitfield;
|
||
unsigned int array[CpuNumOfUints];
|
||
} i386_cpu_flags;
|
||
|
||
/* Position of opcode_modifier bits. */
|
||
|
||
enum
|
||
{
|
||
/* has direction bit. */
|
||
D = 0,
|
||
/* set if operands can be both bytes and words/dwords/qwords, encoded the
|
||
canonical way; the base_opcode field should hold the encoding for byte
|
||
operands */
|
||
W,
|
||
/* load form instruction. Must be placed before store form. */
|
||
Load,
|
||
/* insn has a modrm byte. */
|
||
Modrm,
|
||
/* special case for jump insns; value has to be 1 */
|
||
#define JUMP 1
|
||
/* call and jump */
|
||
#define JUMP_DWORD 2
|
||
/* loop and jecxz */
|
||
#define JUMP_BYTE 3
|
||
/* special case for intersegment leaps/calls */
|
||
#define JUMP_INTERSEGMENT 4
|
||
/* absolute address for jump */
|
||
#define JUMP_ABSOLUTE 5
|
||
Jump,
|
||
/* FP insn memory format bit, sized by 0x4 */
|
||
FloatMF,
|
||
/* needs size prefix if in 32-bit mode */
|
||
#define SIZE16 1
|
||
/* needs size prefix if in 16-bit mode */
|
||
#define SIZE32 2
|
||
/* needs size prefix if in 64-bit mode */
|
||
#define SIZE64 3
|
||
Size,
|
||
/* Check that operand sizes match. */
|
||
CheckOperandSize,
|
||
/* any memory size */
|
||
#define ANY_SIZE 1
|
||
/* fake an extra reg operand for clr, imul and special register
|
||
processing for some instructions. */
|
||
#define REG_KLUDGE 2
|
||
/* deprecated fp insn, gets a warning */
|
||
#define UGH 3
|
||
/* An implicit xmm0 as the first operand */
|
||
#define IMPLICIT_1ST_XMM0 4
|
||
/* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4.
|
||
It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3).
|
||
*/
|
||
#define IMPLICIT_QUAD_GROUP 5
|
||
/* Default mask isn't allowed. */
|
||
#define NO_DEFAULT_MASK 6
|
||
/* Address prefix changes register operand */
|
||
#define ADDR_PREFIX_OP_REG 7
|
||
/* Instrucion requires that destination must be distinct from source
|
||
registers. */
|
||
#define DISTINCT_DEST 8
|
||
/* Instruction updates stack pointer implicitly. */
|
||
#define IMPLICIT_STACK_OP 9
|
||
OperandConstraint,
|
||
/* instruction ignores operand size prefix and in Intel mode ignores
|
||
mnemonic size suffix check. */
|
||
#define IGNORESIZE 1
|
||
/* default insn size depends on mode */
|
||
#define DEFAULTSIZE 2
|
||
MnemonicSize,
|
||
/* b suffix on instruction illegal */
|
||
No_bSuf,
|
||
/* w suffix on instruction illegal */
|
||
No_wSuf,
|
||
/* l suffix on instruction illegal */
|
||
No_lSuf,
|
||
/* s suffix on instruction illegal */
|
||
No_sSuf,
|
||
/* q suffix on instruction illegal */
|
||
No_qSuf,
|
||
/* instruction needs FWAIT */
|
||
FWait,
|
||
/* IsString provides for a quick test for string instructions, and
|
||
its actual value also indicates which of the operands (if any)
|
||
requires use of the %es segment. */
|
||
#define IS_STRING_ES_OP0 2
|
||
#define IS_STRING_ES_OP1 3
|
||
IsString,
|
||
/* RegMem is for instructions with a modrm byte where the register
|
||
destination operand should be encoded in the mod and regmem fields.
|
||
Normally, it will be encoded in the reg field. We add a RegMem
|
||
flag to indicate that it should be encoded in the regmem field. */
|
||
RegMem,
|
||
/* quick test if branch instruction is MPX supported */
|
||
BNDPrefixOk,
|
||
#define PrefixNone 0
|
||
#define PrefixRep 1
|
||
#define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */
|
||
#define PrefixNoTrack 3
|
||
/* Prefixes implying "LOCK okay" must come after Lock. All others have
|
||
to come before. */
|
||
#define PrefixLock 4
|
||
#define PrefixHLELock 5 /* Okay with a LOCK prefix. */
|
||
#define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */
|
||
PrefixOk,
|
||
/* opcode is a prefix */
|
||
IsPrefix,
|
||
/* instruction has extension in 8 bit imm */
|
||
ImmExt,
|
||
/* instruction don't need Rex64 prefix. */
|
||
NoRex64,
|
||
/* insn has VEX prefix:
|
||
1: 128bit VEX prefix (or operand dependent).
|
||
2: 256bit VEX prefix.
|
||
3: Scalar VEX prefix.
|
||
*/
|
||
#define VEX128 1
|
||
#define VEX256 2
|
||
#define VEXScalar 3
|
||
Vex,
|
||
/* How to encode VEX.vvvv:
|
||
1: VEX.vvvv encodes the src1 register operand.
|
||
2: VEX.vvvv encodes the src2 register operand.
|
||
3: VEX.vvvv encodes the dest register operand.
|
||
*/
|
||
#define VexVVVV_SRC1 1
|
||
#define VexVVVV_SRC2 2
|
||
#define VexVVVV_DST 3
|
||
|
||
VexVVVV,
|
||
/* How the VEX.W bit is used:
|
||
0: Set by the REX.W bit.
|
||
1: VEX.W0. Should always be 0.
|
||
2: VEX.W1. Should always be 1.
|
||
3: VEX.WIG. The VEX.W bit is ignored.
|
||
*/
|
||
#define VEXW0 1
|
||
#define VEXW1 2
|
||
#define VEXWIG 3
|
||
VexW,
|
||
/* Opcode prefix (values chosen to be usable directly in
|
||
VEX/XOP/EVEX pp fields):
|
||
0: None
|
||
1: Add 0x66 opcode prefix.
|
||
2: Add 0xf3 opcode prefix.
|
||
3: Add 0xf2 opcode prefix.
|
||
*/
|
||
#define PREFIX_NONE 0
|
||
#define PREFIX_0X66 1
|
||
#define PREFIX_0XF3 2
|
||
#define PREFIX_0XF2 3
|
||
OpcodePrefix,
|
||
/* Instruction with a mandatory SIB byte:
|
||
1: 128bit vector register.
|
||
2: 256bit vector register.
|
||
3: 512bit vector register.
|
||
*/
|
||
#define VECSIB128 1
|
||
#define VECSIB256 2
|
||
#define VECSIB512 3
|
||
#define SIBMEM 4
|
||
SIB,
|
||
|
||
/* SSE to AVX support required */
|
||
SSE2AVX,
|
||
|
||
/* insn has EVEX prefix:
|
||
1: 512bit EVEX prefix.
|
||
2: 128bit EVEX prefix.
|
||
3: 256bit EVEX prefix.
|
||
4: Length-ignored (LIG) EVEX prefix.
|
||
5: Length determined from actual operands.
|
||
6: L'L = 3 (reserved, .insn only)
|
||
*/
|
||
#define EVEX512 1
|
||
#define EVEX128 2
|
||
#define EVEX256 3
|
||
#define EVEXLIG 4
|
||
#define EVEXDYN 5
|
||
#define EVEX_L3 6
|
||
EVex,
|
||
|
||
/* AVX512 masking support */
|
||
Masking,
|
||
|
||
/* AVX512 broadcast support. The number of bytes to broadcast is
|
||
1 << (Broadcast - 1):
|
||
1: Byte broadcast.
|
||
2: Word broadcast.
|
||
3: Dword broadcast.
|
||
4: Qword broadcast.
|
||
*/
|
||
#define BYTE_BROADCAST 1
|
||
#define WORD_BROADCAST 2
|
||
#define DWORD_BROADCAST 3
|
||
#define QWORD_BROADCAST 4
|
||
Broadcast,
|
||
|
||
/* Static rounding control is supported. */
|
||
StaticRounding,
|
||
|
||
/* Supress All Exceptions is supported. */
|
||
SAE,
|
||
|
||
/* Compressed Disp8*N attribute. */
|
||
#define DISP8_SHIFT_VL 7
|
||
Disp8MemShift,
|
||
|
||
/* Support encoding optimization. */
|
||
Optimize,
|
||
|
||
/* Language dialect. NOTE: Order matters! */
|
||
#define INTEL_SYNTAX 1
|
||
#define ATT_SYNTAX 2
|
||
#define ATT_MNEMONIC 3
|
||
Dialect,
|
||
|
||
/* ISA64: Don't change the order without other code adjustments.
|
||
0: Common to AMD64 and Intel64.
|
||
1: AMD64.
|
||
2: Intel64.
|
||
3: Only in Intel64.
|
||
*/
|
||
#define AMD64 1
|
||
#define INTEL64 2
|
||
#define INTEL64ONLY 3
|
||
ISA64,
|
||
|
||
/* egprs (r16-r31) on instruction illegal. We also use it to judge
|
||
whether the instruction supports pseudo-prefix {rex2}. */
|
||
NoEgpr,
|
||
|
||
/* No CSPAZO flags update indication. */
|
||
NF,
|
||
|
||
/* Instrucion requires REX2 prefix. */
|
||
Rex2,
|
||
|
||
/* The last bitfield in i386_opcode_modifier. */
|
||
Opcode_Modifier_Num
|
||
};
|
||
|
||
typedef struct i386_opcode_modifier
|
||
{
|
||
unsigned int d:1;
|
||
unsigned int w:1;
|
||
unsigned int load:1;
|
||
unsigned int modrm:1;
|
||
unsigned int jump:3;
|
||
unsigned int floatmf:1;
|
||
unsigned int size:2;
|
||
unsigned int checkoperandsize:1;
|
||
unsigned int operandconstraint:4;
|
||
unsigned int mnemonicsize:2;
|
||
unsigned int no_bsuf:1;
|
||
unsigned int no_wsuf:1;
|
||
unsigned int no_lsuf:1;
|
||
unsigned int no_ssuf:1;
|
||
unsigned int no_qsuf:1;
|
||
unsigned int fwait:1;
|
||
unsigned int isstring:2;
|
||
unsigned int regmem:1;
|
||
unsigned int bndprefixok:1;
|
||
unsigned int prefixok:3;
|
||
unsigned int isprefix:1;
|
||
unsigned int immext:1;
|
||
unsigned int norex64:1;
|
||
unsigned int vex:2;
|
||
unsigned int vexvvvv:2;
|
||
unsigned int vexw:2;
|
||
unsigned int opcodeprefix:2;
|
||
unsigned int sib:3;
|
||
unsigned int sse2avx:1;
|
||
unsigned int evex:3;
|
||
unsigned int masking:1;
|
||
unsigned int broadcast:3;
|
||
unsigned int staticrounding:1;
|
||
unsigned int sae:1;
|
||
unsigned int disp8memshift:3;
|
||
unsigned int optimize:1;
|
||
unsigned int dialect:2;
|
||
unsigned int isa64:2;
|
||
unsigned int noegpr:1;
|
||
unsigned int nf:1;
|
||
unsigned int rex2:1;
|
||
} i386_opcode_modifier;
|
||
|
||
/* Operand classes. */
|
||
|
||
#define CLASS_WIDTH 4
|
||
enum operand_class
|
||
{
|
||
ClassNone,
|
||
Reg, /* GPRs and FP regs, distinguished by operand size */
|
||
SReg, /* Segment register */
|
||
RegCR, /* Control register */
|
||
RegDR, /* Debug register */
|
||
RegTR, /* Test register */
|
||
RegMMX, /* MMX register */
|
||
RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */
|
||
RegMask, /* Vector Mask register */
|
||
RegBND, /* Bound register */
|
||
};
|
||
|
||
/* Special operand instances. */
|
||
|
||
#define INSTANCE_WIDTH 3
|
||
enum operand_instance
|
||
{
|
||
InstanceNone,
|
||
Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */
|
||
RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */
|
||
RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */
|
||
RegB, /* %bl / %bx / %ebx / %rbx */
|
||
};
|
||
|
||
/* Position of operand_type bits. */
|
||
|
||
enum
|
||
{
|
||
/* Class and Instance */
|
||
ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1,
|
||
/* 1 bit immediate */
|
||
Imm1,
|
||
/* 8 bit immediate */
|
||
Imm8,
|
||
/* 8 bit immediate sign extended */
|
||
Imm8S,
|
||
/* 16 bit immediate */
|
||
Imm16,
|
||
/* 32 bit immediate */
|
||
Imm32,
|
||
/* 32 bit immediate sign extended */
|
||
Imm32S,
|
||
/* 64 bit immediate */
|
||
Imm64,
|
||
/* 8bit/16bit/32bit displacements are used in different ways,
|
||
depending on the instruction. For jumps, they specify the
|
||
size of the PC relative displacement, for instructions with
|
||
memory operand, they specify the size of the offset relative
|
||
to the base register, and for instructions with memory offset
|
||
such as `mov 1234,%al' they specify the size of the offset
|
||
relative to the segment base. */
|
||
/* 8 bit displacement */
|
||
Disp8,
|
||
/* 16 bit displacement */
|
||
Disp16,
|
||
/* 32 bit displacement (64-bit: sign-extended) */
|
||
Disp32,
|
||
/* 64 bit displacement */
|
||
Disp64,
|
||
/* Register which can be used for base or index in memory operand. */
|
||
BaseIndex,
|
||
/* BYTE size. */
|
||
Byte,
|
||
/* WORD size. 2 byte */
|
||
Word,
|
||
/* DWORD size. 4 byte */
|
||
Dword,
|
||
/* FWORD size. 6 byte */
|
||
Fword,
|
||
/* QWORD size. 8 byte */
|
||
Qword,
|
||
/* TBYTE size. 10 byte */
|
||
Tbyte,
|
||
/* XMMWORD size. */
|
||
Xmmword,
|
||
/* YMMWORD size. */
|
||
Ymmword,
|
||
/* ZMMWORD size. */
|
||
Zmmword,
|
||
/* TMMWORD size. */
|
||
Tmmword,
|
||
/* Unspecified memory size. */
|
||
Unspecified,
|
||
|
||
/* The number of bits in i386_operand_type. */
|
||
OTNum
|
||
};
|
||
|
||
#define OTNumOfUints \
|
||
((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1)
|
||
#define OTNumOfBits \
|
||
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
||
|
||
/* If you get a compiler error for zero width of the unused field,
|
||
comment it out. */
|
||
#define OTUnused OTNum
|
||
|
||
typedef union i386_operand_type
|
||
{
|
||
struct
|
||
{
|
||
unsigned int class:CLASS_WIDTH;
|
||
unsigned int instance:INSTANCE_WIDTH;
|
||
unsigned int imm1:1;
|
||
unsigned int imm8:1;
|
||
unsigned int imm8s:1;
|
||
unsigned int imm16:1;
|
||
unsigned int imm32:1;
|
||
unsigned int imm32s:1;
|
||
unsigned int imm64:1;
|
||
unsigned int disp8:1;
|
||
unsigned int disp16:1;
|
||
unsigned int disp32:1;
|
||
unsigned int disp64:1;
|
||
unsigned int baseindex:1;
|
||
unsigned int byte:1;
|
||
unsigned int word:1;
|
||
unsigned int dword:1;
|
||
unsigned int fword:1;
|
||
unsigned int qword:1;
|
||
unsigned int tbyte:1;
|
||
unsigned int xmmword:1;
|
||
unsigned int ymmword:1;
|
||
unsigned int zmmword:1;
|
||
unsigned int tmmword:1;
|
||
unsigned int unspecified:1;
|
||
#ifdef OTUnused
|
||
unsigned int unused:(OTNumOfBits - OTUnused);
|
||
#endif
|
||
} bitfield;
|
||
unsigned int array[OTNumOfUints];
|
||
} i386_operand_type;
|
||
|
||
typedef struct insn_template
|
||
{
|
||
/* instruction name sans width suffix ("mov" for movl insns) */
|
||
unsigned int mnem_off;
|
||
|
||
/* Bitfield arrangement is such that individual fields can be easily
|
||
extracted (in native builds at least) - either by at most a masking
|
||
operation (base_opcode, operands), or by just a (signed) right shift
|
||
(extension_opcode). Please try to maintain this property. */
|
||
|
||
/* base_opcode is the fundamental opcode byte without optional
|
||
prefix(es). */
|
||
unsigned int base_opcode:16;
|
||
#define Opcode_D 0x2 /* Direction bit:
|
||
set if Reg --> Regmem;
|
||
unset if Regmem --> Reg. */
|
||
#define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */
|
||
#define Opcode_FloatD 0x4 /* Direction bit for float insns. */
|
||
#define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */
|
||
#define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */
|
||
/* The next value is arbitrary, as long as it's non-zero and distinct
|
||
from all other values above. */
|
||
#define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */
|
||
|
||
/* how many operands */
|
||
unsigned int operands:3;
|
||
|
||
/* opcode space */
|
||
unsigned int opcode_space:4;
|
||
/* Opcode encoding space (values chosen to be usable directly in
|
||
VEX/XOP mmmmm and EVEX mm fields):
|
||
0: Base opcode space.
|
||
1: 0F opcode prefix / space.
|
||
2: 0F38 opcode prefix / space.
|
||
3: 0F3A opcode prefix / space.
|
||
4: EVEXMAP4 opcode prefix / space.
|
||
5: EVEXMAP5 opcode prefix / space.
|
||
6: EVEXMAP6 opcode prefix / space.
|
||
7: VEXMAP7 opcode prefix / space.
|
||
8: XOP 08 opcode space.
|
||
9: XOP 09 opcode space.
|
||
A: XOP 0A opcode space.
|
||
*/
|
||
#define SPACE_BASE 0
|
||
#define SPACE_0F 1
|
||
#define SPACE_0F38 2
|
||
#define SPACE_0F3A 3
|
||
#define SPACE_EVEXMAP4 4
|
||
#define SPACE_EVEXMAP5 5
|
||
#define SPACE_EVEXMAP6 6
|
||
#define SPACE_VEXMAP7 7
|
||
#define SPACE_XOP08 8
|
||
#define SPACE_XOP09 9
|
||
#define SPACE_XOP0A 0xA
|
||
|
||
/* (Fake) base opcode value for pseudo prefixes. */
|
||
#define PSEUDO_PREFIX 0
|
||
|
||
/* extension_opcode is the 3 bit extension for group <n> insns.
|
||
This field is also used to store the 8-bit opcode suffix for the
|
||
AMD 3DNow! instructions.
|
||
If this template has no extension opcode (the usual case) use None
|
||
Instructions */
|
||
signed int extension_opcode:9;
|
||
#define None (-1) /* If no extension_opcode is possible. */
|
||
|
||
/* Pseudo prefixes. */
|
||
#define Prefix_Disp8 0 /* {disp8} */
|
||
#define Prefix_Disp16 1 /* {disp16} */
|
||
#define Prefix_Disp32 2 /* {disp32} */
|
||
#define Prefix_Load 3 /* {load} */
|
||
#define Prefix_Store 4 /* {store} */
|
||
#define Prefix_VEX 5 /* {vex} */
|
||
#define Prefix_VEX3 6 /* {vex3} */
|
||
#define Prefix_EVEX 7 /* {evex} */
|
||
#define Prefix_REX 8 /* {rex} */
|
||
#define Prefix_REX2 9 /* {rex2} */
|
||
#define Prefix_NoOptimize 10 /* {nooptimize} */
|
||
#define Prefix_NF 11 /* {nf} */
|
||
|
||
/* the bits in opcode_modifier are used to generate the final opcode from
|
||
the base_opcode. These bits also are used to detect alternate forms of
|
||
the same instruction */
|
||
i386_opcode_modifier opcode_modifier;
|
||
|
||
/* cpu feature attributes */
|
||
i386_cpu_attr cpu, cpu_any;
|
||
|
||
/* operand_types[i] describes the type of operand i. This is made
|
||
by OR'ing together all of the possible type masks. (e.g.
|
||
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
||
either a register or an immediate operand. */
|
||
i386_operand_type operand_types[MAX_OPERANDS];
|
||
}
|
||
insn_template;
|
||
|
||
/* these are for register name --> number & type hash lookup */
|
||
typedef struct
|
||
{
|
||
char reg_name[8];
|
||
i386_operand_type reg_type;
|
||
unsigned char reg_flags;
|
||
#define RegRex 0x1 /* Extended register. */
|
||
#define RegRex64 0x2 /* Extended 8 bit register. */
|
||
#define RegVRex 0x4 /* Extended vector register. */
|
||
#define RegRex2 0x8 /* Extended GPRs R16–R31 register. */
|
||
unsigned char reg_num;
|
||
#define RegIP ((unsigned char ) ~0)
|
||
/* EIZ and RIZ are fake index registers. */
|
||
#define RegIZ (RegIP - 1)
|
||
/* FLAT is a fake segment register (Intel mode). */
|
||
#define RegFlat ((unsigned char) ~0)
|
||
unsigned char dw2_regnum[2];
|
||
#define Dw2Inval 0xff
|
||
}
|
||
reg_entry;
|