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ed443b61e1
When I exercise GDBserver software single step, I see the following error, which has been already handled by GDB properly. In GDBserver log, we can see, GDBserver tries to single step instruction on 0xb6e0a6e4, and destination address is 0xffff0fe0, stop pc is 0xb6e0a6e4 Writing f001f0e7 to 0xffff0fe0 in process 7132 Failed to insert breakpoint at 0xffff0fe0 (Input/output error). Failed to insert breakpoint at 0xffff0fe0 (-1). (gdb) disassemble __aeabi_read_tp,+8 Dump of assembler code from 0xb6e0a6e0 to 0xb6e0a6e8: 0xb6e0a6e0 <__aeabi_read_tp+0>: mvn r0, #61440 ; 0xf000 0xb6e0a6e4 <__aeabi_read_tp+4>: sub pc, r0, #31 however, it fails inserting breakpoint there. This problem has already fixed by GDB, see comments in arm-linux-tdep.c:arm_linux_software_single_step /* The Linux kernel offers some user-mode helpers in a high page. We can not read this page (as of 2.6.23), and even if we could then we couldn't set breakpoints in it, and even if we could then the atomic operations would fail when interrupted. They are all called as functions and return to the address in LR, so step to there instead. */ so we need to do the same thing in GDB side as well. This patch adds a new field fixup in arm_get_next_pcs_ops, so that we can fix up PC for arm-linux target. In this way, both GDB and GDBserver can single step instructions going to kernel helpers. gdb: 2016-02-12 Yao Qi <yao.qi@linaro.org> * arch/arm-get-next-pcs.c (arm_get_next_pcs): Call self->ops->fixup if it isn't NULL. * arch/arm-get-next-pcs.h: Include gdb_vecs.h. (struct arm_get_next_pcs_ops) <fixup>: New field. * arch/arm-linux.c: Include common-regcache.h and arch/arm-get-next-pcs.h. (arm_linux_get_next_pcs_fixup): New function. * arch/arm-linux.h (arm_linux_get_next_pcs_fixup): Declare. * arm-linux-tdep.c (arm_linux_get_next_pcs_ops): Initialize it with arm_linux_get_next_pcs_fixup. (arm_linux_software_single_step): Move code to arm_linux_get_next_pcs_fixup. * arm-tdep.c (arm_get_next_pcs_ops): Initialize it. gdb/gdbserver: 2016-02-12 Yao Qi <yao.qi@linaro.org> * linux-arm-low.c (get_next_pcs_ops): Initialize it with arm_linux_get_next_pcs_fixup.
79 lines
3.0 KiB
C
79 lines
3.0 KiB
C
/* Common target dependent code for GNU/Linux on ARM systems.
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Copyright (C) 1999-2016 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef ARM_LINUX_H
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#define ARM_LINUX_H
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/* There are a couple of different possible stack layouts that
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we need to support.
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Before version 2.6.18, the kernel used completely independent
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layouts for non-RT and RT signals. For non-RT signals the stack
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began directly with a struct sigcontext. For RT signals the stack
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began with two redundant pointers (to the siginfo and ucontext),
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and then the siginfo and ucontext.
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As of version 2.6.18, the non-RT signal frame layout starts with
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a ucontext and the RT signal frame starts with a siginfo and then
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a ucontext. Also, the ucontext now has a designated save area
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for coprocessor registers.
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For RT signals, it's easy to tell the difference: we look for
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pinfo, the pointer to the siginfo. If it has the expected
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value, we have an old layout. If it doesn't, we have the new
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layout.
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For non-RT signals, it's a bit harder. We need something in one
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layout or the other with a recognizable offset and value. We can't
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use the return trampoline, because ARM usually uses SA_RESTORER,
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in which case the stack return trampoline is not filled in.
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We can't use the saved stack pointer, because sigaltstack might
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be in use. So for now we guess the new layout... */
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/* There are three words (trap_no, error_code, oldmask) in
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struct sigcontext before r0. */
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#define ARM_SIGCONTEXT_R0 0xc
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/* There are five words (uc_flags, uc_link, and three for uc_stack)
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in the ucontext_t before the sigcontext. */
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#define ARM_UCONTEXT_SIGCONTEXT 0x14
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/* There are three elements in an rt_sigframe before the ucontext:
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pinfo, puc, and info. The first two are pointers and the third
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is a struct siginfo, with size 128 bytes. We could follow puc
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to the ucontext, but it's simpler to skip the whole thing. */
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#define ARM_OLD_RT_SIGFRAME_SIGINFO 0x8
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#define ARM_OLD_RT_SIGFRAME_UCONTEXT 0x88
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#define ARM_NEW_RT_SIGFRAME_UCONTEXT 0x80
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#define ARM_NEW_SIGFRAME_MAGIC 0x5ac3c35a
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int
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arm_linux_sigreturn_next_pc_offset (unsigned long sp,
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unsigned long sp_data,
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unsigned long svc_number,
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int is_sigreturn);
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struct arm_get_next_pcs;
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CORE_ADDR arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
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CORE_ADDR pc);
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#endif /* ARM_LINUX_H */
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