binutils-gdb/include
srinath de7a30ceaa aarch64: Add support for sve2p1 pmov instruction.
This patch adds support for followign SVE2p1 instruction, spec is available here [1].

1. PMOV (to vector)
2. PMOV (to predicate)

Both pmov (to vector) and pmov (to predicate) have destination scalable vector
register and source scalable vector register respectively as an operand with no
suffix and optional index. To handle this case we have added 8 new operands in
this patch.

AARCH64_OPND_SVE_Zn0_INDEX,      /* Zn[index], bits [9:5].  */
AARCH64_OPND_SVE_Zn1_17_INDEX,    /* Zn[index], bits [9:5,17].  */
AARCH64_OPND_SVE_Zn2_18_INDEX,    /* Zn[index], bits [9:5,18:17].  */
AARCH64_OPND_SVE_Zn3_22_INDEX,    /* Zn[index], bits [9:5,18:17,22].  */
AARCH64_OPND_SVE_Zd0_INDEX,      /* Zn[index], bits [4:0].  */
AARCH64_OPND_SVE_Zd1_17_INDEX,    /* Zn[index], bits [4:0,17].  */
AARCH64_OPND_SVE_Zd2_18_INDEX,    /* Zn[index], bits [4:0,18:17].  */
AARCH64_OPND_SVE_Zd3_22_INDEX,    /* Zn[index], bits [4:0,18:17,22].  */

Since the index of the <Zd> operand is optional, the index part is
dropped in disassembly in both the cases of "no index" or "zero index".

As per spec: PMOV <Zd>{[<imm>]}, <Pn>.D
             PMOV <Pn>.D, <Zd>{[<imm>]}

Example1:
	Assembly: pmov z5[0], p6.d
	Disassembly: pmov z5, p6.d

        Assembly: pmov z5, p6.d
        Disassembly: pmov z5, p6.d

Example2:
	Assembly: pmov p4.b, z5[0]
	Disassembly: pmov p4.b, z5

        Assembly: pmov p4.b, z5
        Disassembly: pmov p4.b, z5
[1]: https://developer.arm.com/documentation/ddi0602/2024-03/SVE-Instructions?lang=en
2024-07-08 17:48:23 +01:00
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aout Update year range in copyright notice of binutils files 2024-01-04 22:58:12 +10:30
cgen Update year range in copyright notice of binutils files 2024-01-04 22:58:12 +10:30
coff riscv64-pei uninitialised data writing relocs 2024-01-25 08:41:14 +10:30
elf gdb: LoongArch: Add support for hardware breakpoint 2024-06-25 05:50:29 +08:00
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mach-o Update year range in copyright notice of binutils files 2024-01-04 22:58:12 +10:30
opcode aarch64: Add support for sve2p1 pmov instruction. 2024-07-08 17:48:23 +01:00
sim sim: Fix -Werror=shadow=local by changing mem to addr in sim_{read,write} 2024-01-22 14:22:30 +01:00
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ChangeLog gdb: ignore -Wregister instead of -Wdeprecated-register 2024-04-07 22:57:39 -04:00
ChangeLog-0415 binutils ChangeLog rotation 2016-01-01 22:59:17 +10:30
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