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ae440402f5
Reported by Rich Felker when building on 32-bit hosts. Backwards jump negative offsets were not calculated correctly due to improper 32-bit to 64-bit zero-extension. The 64-bit fields are present because we are mixing 32-bit and 64-bit architectures in our cpu descriptions. Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture spec for 64-bit but no implementations or simulators. My thought is if we need them in the future we should do the proper work to support both 32-bit and 64-bit implementations co-existing then. cpu/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> PR 25184 * or1k.cpu (arch or1k): Remove or64 and or64nd machs. (ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros. (cpu or1k64bf, mach or64, mach or64nd): Remove definitions. * or1kcommon.cpu (h-fdr): Remove hardware. * or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions. (float-regreg-insn): Remove lf- mnemonic -d instruction pattern. (float-setflag-insn-base): Remove lf-sf mnemonic -d pattern. (float-cust-insn): Remove "lf-cust" cust-num "-d" pattern. (lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
104 lines
3.0 KiB
Scheme
104 lines
3.0 KiB
Scheme
; OpenRISC 1000 architecture. -*- Scheme -*-
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; Copyright 2000-2019 Free Software Foundation, Inc.
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; Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org
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; Modified by Julius Baxter, juliusbaxter@gmail.com
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; Modified by Peter Gavin, pgavin@gmail.com
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; Modified by Andrey Bacherov, avbacherov@opencores.org
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;
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; This program is free software; you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation; either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program; if not, see <http://www.gnu.org/licenses/>
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(include "simplify.inc")
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; The OpenRISC family is a set of RISC microprocessor architectures with an
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; emphasis on scalability and is targetted at embedded use.
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; The CPU RTL development is a collaborative open source effort.
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; http://opencores.org/or1k
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; http://openrisc.net
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(define-arch
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(name or1k)
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(comment "OpenRISC 1000")
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(default-alignment aligned)
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(insn-lsb0? #t)
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(machs or32 or32nd)
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(isas openrisc)
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)
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; Instruction set parameters.
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(define-isa
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; Name of the ISA.
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(name openrisc)
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; Base insturction length. The insns are always 32 bits wide.
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(base-insn-bitsize 32)
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)
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(define-pmacro OR32-MACHS or32,or32nd)
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(define-pmacro ORBIS-MACHS or32,or32nd)
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(define-pmacro ORFPX32-MACHS or32,or32nd)
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(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
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(define-attr
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(for model)
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(type boolean)
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(name NO-DELAY-SLOT)
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(comment "does not have delay slots")
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)
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(if (keep-mach? (or32 or32nd))
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(begin
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(define-cpu
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(name or1k32bf)
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(comment "OpenRISC 1000 32-bit CPU family")
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(insn-endian big)
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(data-endian big)
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(word-bitsize 32)
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(file-transform "")
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)
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(define-mach
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(name or32)
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(comment "Generic OpenRISC 1000 32-bit CPU")
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(cpu or1k32bf)
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(bfd-name "or1k")
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)
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(define-mach
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(name or32nd)
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(comment "Generic OpenRISC 1000 32-bit CPU with no branch delay slot")
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(cpu or1k32bf)
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(bfd-name "or1knd")
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)
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; OpenRISC 1200 - 32-bit or1k CPU implementation
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(define-model
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(name or1200) (comment "OpenRISC 1200 model")
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(attrs)
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(mach or32)
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(unit u-exec "Execution Unit" () 1 1 () () () ())
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)
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; OpenRISC 1200 - 32-bit or1k CPU implementation
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(define-model
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(name or1200nd) (comment "OpenRISC 1200 model with no branch delay slot")
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(attrs NO-DELAY-SLOT)
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(mach or32nd)
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(unit u-exec "Execution Unit" () 1 1 () () () ())
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)
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)
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)
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(include "or1kcommon.cpu")
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(include "or1korbis.cpu")
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(include "or1korfpx.cpu")
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