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729 lines
19 KiB
C
729 lines
19 KiB
C
/* Disassembly routines for TMS320C30 architecture
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Copyright (C) 1998-2019 Free Software Foundation, Inc.
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Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <errno.h>
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#include <math.h>
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#include "disassemble.h"
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#include "opcode/tic30.h"
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#define NORMAL_INSN 1
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#define PARALLEL_INSN 2
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/* Gets the type of instruction based on the top 2 or 3 bits of the
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instruction word. */
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#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
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/* Instruction types. */
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#define TWO_OPERAND_1 0x00000000
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#define TWO_OPERAND_2 0x40000000
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#define THREE_OPERAND 0x20000000
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#define PAR_STORE 0xC0000000
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#define MUL_ADDS 0x80000000
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#define BRANCHES 0x60000000
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/* Specific instruction id bits. */
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#define NORMAL_IDEN 0x1F800000
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#define PAR_STORE_IDEN 0x3E000000
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#define MUL_ADD_IDEN 0x2C000000
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#define BR_IMM_IDEN 0x1F000000
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#define BR_COND_IDEN 0x1C3F0000
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/* Addressing modes. */
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#define AM_REGISTER 0x00000000
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#define AM_DIRECT 0x00200000
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#define AM_INDIRECT 0x00400000
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#define AM_IMM 0x00600000
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#define P_FIELD 0x03000000
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#define REG_AR0 0x08
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#define LDP_INSN 0x08700000
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/* TMS320C30 program counter for current instruction. */
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static unsigned int _pc;
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struct instruction
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{
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int type;
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insn_template *tm;
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partemplate *ptm;
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};
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static int
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get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
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{
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switch (GET_TYPE (insn_word))
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{
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case TWO_OPERAND_1:
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case TWO_OPERAND_2:
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case THREE_OPERAND:
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insn->type = NORMAL_INSN;
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{
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insn_template *current_optab = (insn_template *) tic30_optab;
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for (; current_optab < tic30_optab_end; current_optab++)
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{
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if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
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{
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if (current_optab->operands == 0)
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{
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if (current_optab->base_opcode == insn_word)
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{
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insn->tm = current_optab;
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break;
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}
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}
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else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
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{
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insn->tm = current_optab;
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break;
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}
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}
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}
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}
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break;
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case PAR_STORE:
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insn->type = PARALLEL_INSN;
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{
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partemplate *current_optab = (partemplate *) tic30_paroptab;
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for (; current_optab < tic30_paroptab_end; current_optab++)
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{
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if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
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{
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if ((current_optab->base_opcode & PAR_STORE_IDEN)
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== (insn_word & PAR_STORE_IDEN))
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{
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insn->ptm = current_optab;
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break;
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}
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}
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}
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}
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break;
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case MUL_ADDS:
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insn->type = PARALLEL_INSN;
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{
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partemplate *current_optab = (partemplate *) tic30_paroptab;
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for (; current_optab < tic30_paroptab_end; current_optab++)
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{
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if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
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{
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if ((current_optab->base_opcode & MUL_ADD_IDEN)
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== (insn_word & MUL_ADD_IDEN))
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{
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insn->ptm = current_optab;
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break;
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}
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}
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}
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}
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break;
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case BRANCHES:
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insn->type = NORMAL_INSN;
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{
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insn_template *current_optab = (insn_template *) tic30_optab;
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for (; current_optab < tic30_optab_end; current_optab++)
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{
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if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
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{
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if (current_optab->operand_types[0] & Imm24)
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{
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if ((current_optab->base_opcode & BR_IMM_IDEN)
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== (insn_word & BR_IMM_IDEN))
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{
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insn->tm = current_optab;
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break;
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}
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}
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else if (current_optab->operands > 0)
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{
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if ((current_optab->base_opcode & BR_COND_IDEN)
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== (insn_word & BR_COND_IDEN))
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{
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insn->tm = current_optab;
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break;
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}
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}
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else
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{
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if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
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== (insn_word & (BR_COND_IDEN | 0x00800000)))
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{
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insn->tm = current_optab;
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break;
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}
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}
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}
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}
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}
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break;
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default:
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return 0;
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}
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return 1;
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}
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#define OPERAND_BUFFER_LEN 15
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static int
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get_register_operand (unsigned char fragment, char *buffer)
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{
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const reg *current_reg = tic30_regtab;
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if (buffer == NULL)
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return 0;
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for (; current_reg < tic30_regtab_end; current_reg++)
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{
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if ((fragment & 0x1F) == current_reg->opcode)
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{
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strncpy (buffer, current_reg->name, OPERAND_BUFFER_LEN);
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buffer[OPERAND_BUFFER_LEN - 1] = 0;
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return 1;
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}
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}
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return 0;
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}
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static int
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get_indirect_operand (unsigned short fragment,
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int size,
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char *buffer)
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{
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unsigned char mod;
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unsigned arnum;
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unsigned char disp;
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if (buffer == NULL)
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return 0;
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/* Determine which bits identify the sections of the indirect
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operand based on the size in bytes. */
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switch (size)
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{
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case 1:
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mod = (fragment & 0x00F8) >> 3;
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arnum = (fragment & 0x0007);
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disp = 0;
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break;
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case 2:
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mod = (fragment & 0xF800) >> 11;
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arnum = (fragment & 0x0700) >> 8;
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disp = (fragment & 0x00FF);
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break;
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default:
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return 0;
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}
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{
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const ind_addr_type *current_ind = tic30_indaddr_tab;
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for (; current_ind < tic30_indaddrtab_end; current_ind++)
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{
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if (current_ind->modfield == mod)
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{
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if (current_ind->displacement == IMPLIED_DISP && size == 2)
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continue;
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else
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{
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size_t i, len;
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int bufcnt;
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len = strlen (current_ind->syntax);
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for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
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{
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buffer[bufcnt] = current_ind->syntax[i];
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if (bufcnt > 0
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&& bufcnt < OPERAND_BUFFER_LEN - 1
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&& buffer[bufcnt - 1] == 'a'
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&& buffer[bufcnt] == 'r')
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buffer[++bufcnt] = arnum + '0';
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if (bufcnt < OPERAND_BUFFER_LEN - 1
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&& buffer[bufcnt] == '('
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&& current_ind->displacement == DISP_REQUIRED)
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{
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snprintf (buffer + (bufcnt + 1),
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OPERAND_BUFFER_LEN - (bufcnt + 1),
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"%u", disp);
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bufcnt += strlen (buffer + (bufcnt + 1));
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}
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}
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buffer[bufcnt + 1] = '\0';
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break;
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}
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}
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}
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}
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return 1;
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}
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static int
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cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
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{
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unsigned long exponent, sign, mant;
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union
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{
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unsigned long l;
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float f;
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} val;
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if (size == 2)
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{
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if ((tmsfloat & 0x0000F000) == 0x00008000)
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tmsfloat = 0x80000000;
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else
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{
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tmsfloat <<= 16;
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tmsfloat = (long) tmsfloat >> 4;
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}
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}
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exponent = tmsfloat & 0xFF000000;
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if (exponent == 0x80000000)
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{
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*ieeefloat = 0.0;
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return 1;
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}
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exponent += 0x7F000000;
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sign = (tmsfloat & 0x00800000) << 8;
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mant = tmsfloat & 0x007FFFFF;
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if (exponent == 0xFF000000)
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{
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if (mant == 0)
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*ieeefloat = ERANGE;
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#ifdef HUGE_VALF
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if (sign == 0)
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*ieeefloat = HUGE_VALF;
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else
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*ieeefloat = -HUGE_VALF;
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#else
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if (sign == 0)
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*ieeefloat = 1.0 / 0.0;
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else
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*ieeefloat = -1.0 / 0.0;
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#endif
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return 1;
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}
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exponent >>= 1;
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if (sign)
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{
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mant = (~mant) & 0x007FFFFF;
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mant += 1;
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exponent += mant & 0x00800000;
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exponent &= 0x7F800000;
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mant &= 0x007FFFFF;
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}
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if (tmsfloat == 0x80000000)
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sign = mant = exponent = 0;
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tmsfloat = sign | exponent | mant;
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val.l = tmsfloat;
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*ieeefloat = val.f;
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return 1;
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}
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static int
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print_two_operand (disassemble_info *info,
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unsigned long insn_word,
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struct instruction *insn)
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{
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char name[12];
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char operand[2][OPERAND_BUFFER_LEN] =
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{
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{0},
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{0}
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};
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float f_number;
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if (insn->tm == NULL)
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return 0;
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strcpy (name, insn->tm->name);
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if (insn->tm->opcode_modifier == AddressMode)
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{
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int src_op, dest_op;
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/* Determine whether instruction is a store or a normal instruction. */
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if ((insn->tm->operand_types[1] & (Direct | Indirect))
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== (Direct | Indirect))
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{
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src_op = 1;
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dest_op = 0;
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}
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else
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{
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src_op = 0;
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dest_op = 1;
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}
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/* Get the destination register. */
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if (insn->tm->operands == 2)
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get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
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/* Get the source operand based on addressing mode. */
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switch (insn_word & AddressMode)
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{
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case AM_REGISTER:
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/* Check for the NOP instruction before getting the operand. */
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if ((insn->tm->operand_types[0] & NotReq) == 0)
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get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
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break;
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case AM_DIRECT:
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sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
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break;
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case AM_INDIRECT:
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get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
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break;
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case AM_IMM:
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/* Get the value of the immediate operand based on variable type. */
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switch (insn->tm->imm_arg_type)
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{
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case Imm_Float:
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cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
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sprintf (operand[src_op], "%2.2f", f_number);
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break;
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case Imm_SInt:
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sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
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break;
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case Imm_UInt:
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sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
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break;
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default:
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return 0;
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}
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/* Handle special case for LDP instruction. */
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if ((insn_word & 0xFFFFFF00) == LDP_INSN)
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{
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strcpy (name, "ldp");
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sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
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operand[1][0] = '\0';
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}
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}
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}
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/* Handle case for stack and rotate instructions. */
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else if (insn->tm->operands == 1)
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{
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if (insn->tm->opcode_modifier == StackOp)
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get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
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}
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/* Output instruction to stream. */
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info->fprintf_func (info->stream, " %s %s%c%s", name,
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operand[0][0] ? operand[0] : "",
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operand[1][0] ? ',' : ' ',
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operand[1][0] ? operand[1] : "");
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return 1;
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}
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static int
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print_three_operand (disassemble_info *info,
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unsigned long insn_word,
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struct instruction *insn)
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{
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char operand[3][OPERAND_BUFFER_LEN] =
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{
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{0},
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{0},
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{0}
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};
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if (insn->tm == NULL)
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return 0;
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switch (insn_word & AddressMode)
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{
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case AM_REGISTER:
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get_register_operand ((insn_word & 0x000000FF), operand[0]);
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get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
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break;
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case AM_DIRECT:
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get_register_operand ((insn_word & 0x000000FF), operand[0]);
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get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
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break;
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case AM_INDIRECT:
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get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
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get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
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break;
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case AM_IMM:
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get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
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get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
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break;
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default:
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return 0;
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}
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if (insn->tm->operands == 3)
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get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
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info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name,
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operand[0], operand[1],
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operand[2][0] ? ',' : ' ',
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operand[2][0] ? operand[2] : "");
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return 1;
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}
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static int
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print_par_insn (disassemble_info *info,
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unsigned long insn_word,
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struct instruction *insn)
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{
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size_t i, len;
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char *name1, *name2;
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char operand[2][3][OPERAND_BUFFER_LEN] =
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{
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{
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{0},
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{0},
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{0}
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},
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{
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{0},
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{0},
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{0}
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}
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};
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if (insn->ptm == NULL)
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return 0;
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/* Parse out the names of each of the parallel instructions from the
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q_insn1_insn2 format. */
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name1 = (char *) strdup (insn->ptm->name + 2);
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name2 = "";
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len = strlen (name1);
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for (i = 0; i < len; i++)
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{
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if (name1[i] == '_')
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{
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name2 = &name1[i + 1];
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name1[i] = '\0';
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break;
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}
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}
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/* Get the operands of the instruction based on the operand order. */
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switch (insn->ptm->oporder)
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{
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case OO_4op1:
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get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
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get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
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get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
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get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
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break;
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case OO_4op2:
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get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
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get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
|
|
get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
|
|
break;
|
|
case OO_4op3:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
|
|
get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
|
|
break;
|
|
case OO_5op1:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
|
|
get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
|
|
break;
|
|
case OO_5op2:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
|
|
get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
|
|
break;
|
|
case OO_PField:
|
|
if (insn_word & 0x00800000)
|
|
get_register_operand (0x01, operand[0][2]);
|
|
else
|
|
get_register_operand (0x00, operand[0][2]);
|
|
if (insn_word & 0x00400000)
|
|
get_register_operand (0x03, operand[1][2]);
|
|
else
|
|
get_register_operand (0x02, operand[1][2]);
|
|
switch (insn_word & P_FIELD)
|
|
{
|
|
case 0x00000000:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
|
|
break;
|
|
case 0x01000000:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
|
|
break;
|
|
case 0x02000000:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
|
|
break;
|
|
case 0x03000000:
|
|
get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
|
|
get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
|
|
get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
|
|
get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
info->fprintf_func (info->stream, " %s %s,%s%c%s", name1,
|
|
operand[0][0], operand[0][1],
|
|
operand[0][2][0] ? ',' : ' ',
|
|
operand[0][2][0] ? operand[0][2] : "");
|
|
info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
|
|
operand[1][0], operand[1][1],
|
|
operand[1][2][0] ? ',' : ' ',
|
|
operand[1][2][0] ? operand[1][2] : "");
|
|
free (name1);
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
print_branch (disassemble_info *info,
|
|
unsigned long insn_word,
|
|
struct instruction *insn)
|
|
{
|
|
char operand[2][OPERAND_BUFFER_LEN] =
|
|
{
|
|
{0},
|
|
{0}
|
|
};
|
|
unsigned long address;
|
|
int print_label = 0;
|
|
|
|
if (insn->tm == NULL)
|
|
return 0;
|
|
/* Get the operands for 24-bit immediate jumps. */
|
|
if (insn->tm->operand_types[0] & Imm24)
|
|
{
|
|
address = insn_word & 0x00FFFFFF;
|
|
sprintf (operand[0], "0x%lX", address);
|
|
print_label = 1;
|
|
}
|
|
/* Get the operand for the trap instruction. */
|
|
else if (insn->tm->operand_types[0] & IVector)
|
|
{
|
|
address = insn_word & 0x0000001F;
|
|
sprintf (operand[0], "0x%lX", address);
|
|
}
|
|
else
|
|
{
|
|
address = insn_word & 0x0000FFFF;
|
|
/* Get the operands for the DB instructions. */
|
|
if (insn->tm->operands == 2)
|
|
{
|
|
get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
|
|
if (insn_word & PCRel)
|
|
{
|
|
sprintf (operand[1], "%d", (short) address);
|
|
print_label = 1;
|
|
}
|
|
else
|
|
get_register_operand (insn_word & 0x0000001F, operand[1]);
|
|
}
|
|
/* Get the operands for the standard branches. */
|
|
else if (insn->tm->operands == 1)
|
|
{
|
|
if (insn_word & PCRel)
|
|
{
|
|
address = (short) address;
|
|
sprintf (operand[0], "%ld", address);
|
|
print_label = 1;
|
|
}
|
|
else
|
|
get_register_operand (insn_word & 0x0000001F, operand[0]);
|
|
}
|
|
}
|
|
info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name,
|
|
operand[0][0] ? operand[0] : "",
|
|
operand[1][0] ? ',' : ' ',
|
|
operand[1][0] ? operand[1] : "");
|
|
/* Print destination of branch in relation to current symbol. */
|
|
if (print_label && info->symbols)
|
|
{
|
|
asymbol *sym = *info->symbols;
|
|
|
|
if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
|
|
{
|
|
address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
|
|
/* Check for delayed instruction, if so adjust destination. */
|
|
if (insn_word & 0x00200000)
|
|
address += 2;
|
|
}
|
|
else
|
|
{
|
|
address -= ((sym->section->vma + sym->value) / 4);
|
|
}
|
|
if (address == 0)
|
|
info->fprintf_func (info->stream, " <%s>", sym->name);
|
|
else
|
|
info->fprintf_func (info->stream, " <%s %c %lu>", sym->name,
|
|
((short) address < 0) ? '-' : '+',
|
|
address);
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
int
|
|
print_insn_tic30 (bfd_vma pc, disassemble_info *info)
|
|
{
|
|
unsigned long insn_word;
|
|
struct instruction insn = { 0, NULL, NULL };
|
|
bfd_vma bufaddr = pc - info->buffer_vma;
|
|
|
|
/* Obtain the current instruction word from the buffer. */
|
|
insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
|
|
(*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
|
|
_pc = pc / 4;
|
|
/* Get the instruction refered to by the current instruction word
|
|
and print it out based on its type. */
|
|
if (!get_tic30_instruction (insn_word, &insn))
|
|
return -1;
|
|
switch (GET_TYPE (insn_word))
|
|
{
|
|
case TWO_OPERAND_1:
|
|
case TWO_OPERAND_2:
|
|
if (!print_two_operand (info, insn_word, &insn))
|
|
return -1;
|
|
break;
|
|
case THREE_OPERAND:
|
|
if (!print_three_operand (info, insn_word, &insn))
|
|
return -1;
|
|
break;
|
|
case PAR_STORE:
|
|
case MUL_ADDS:
|
|
if (!print_par_insn (info, insn_word, &insn))
|
|
return -1;
|
|
break;
|
|
case BRANCHES:
|
|
if (!print_branch (info, insn_word, &insn))
|
|
return -1;
|
|
break;
|
|
}
|
|
return 4;
|
|
}
|