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d87bef3a7b
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
426 lines
10 KiB
C
426 lines
10 KiB
C
/* Disassembler code for Renesas RL78.
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Copyright (C) 2011-2023 Free Software Foundation, Inc.
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Contributed by Red Hat.
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Written by DJ Delorie.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "bfd.h"
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#include "elf-bfd.h"
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#include "disassemble.h"
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#include "opcode/rl78.h"
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#include "elf/rl78.h"
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#include <setjmp.h>
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#define DEBUG_SEMANTICS 0
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typedef struct
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{
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bfd_vma pc;
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disassemble_info * dis;
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} RL78_Data;
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struct private
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{
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OPCODES_SIGJMP_BUF bailout;
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};
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static int
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rl78_get_byte (void * vdata)
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{
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bfd_byte buf[1];
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RL78_Data *rl78_data = (RL78_Data *) vdata;
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int status;
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status = rl78_data->dis->read_memory_func (rl78_data->pc,
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buf,
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1,
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rl78_data->dis);
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if (status != 0)
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{
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struct private *priv = (struct private *) rl78_data->dis->private_data;
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rl78_data->dis->memory_error_func (status, rl78_data->pc,
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rl78_data->dis);
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OPCODES_SIGLONGJMP (priv->bailout, 1);
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}
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rl78_data->pc ++;
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return buf[0];
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}
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static char const *
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register_names[] =
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{
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"",
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"x", "a", "c", "b", "e", "d", "l", "h",
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"ax", "bc", "de", "hl",
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"sp", "psw", "cs", "es", "pmc", "mem"
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};
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static char const *
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condition_names[] =
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{
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"t", "f", "c", "nc", "h", "nh", "z", "nz"
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};
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static int
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indirect_type (int t)
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{
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switch (t)
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{
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case RL78_Operand_Indirect:
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case RL78_Operand_BitIndirect:
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case RL78_Operand_PostInc:
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case RL78_Operand_PreDec:
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return 1;
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default:
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return 0;
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}
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}
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static int
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print_insn_rl78_common (bfd_vma addr, disassemble_info * dis, RL78_Dis_Isa isa)
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{
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int rv;
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RL78_Data rl78_data;
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RL78_Opcode_Decoded opcode;
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const char * s;
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#if DEBUG_SEMANTICS
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static char buf[200];
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#endif
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struct private priv;
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dis->private_data = &priv;
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rl78_data.pc = addr;
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rl78_data.dis = dis;
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if (OPCODES_SIGSETJMP (priv.bailout) != 0)
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{
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/* Error return. */
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return -1;
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}
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rv = rl78_decode_opcode (addr, &opcode, rl78_get_byte, &rl78_data, isa);
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dis->bytes_per_line = 10;
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#define PR (dis->fprintf_func)
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#define PS (dis->stream)
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#define PC(c) PR (PS, "%c", c)
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s = opcode.syntax;
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#if DEBUG_SEMANTICS
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switch (opcode.id)
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{
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case RLO_unknown: s = "uknown"; break;
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case RLO_add: s = "add: %e0%0 += %e1%1"; break;
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case RLO_addc: s = "addc: %e0%0 += %e1%1 + CY"; break;
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case RLO_and: s = "and: %e0%0 &= %e1%1"; break;
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case RLO_branch: s = "branch: pc = %e0%0"; break;
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case RLO_branch_cond: s = "branch_cond: pc = %e0%0 if %c1 / %e1%1"; break;
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case RLO_branch_cond_clear: s = "branch_cond_clear: pc = %e0%0 if %c1 / %e1%1, %e1%1 = 0"; break;
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case RLO_call: s = "call: pc = %e1%0"; break;
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case RLO_cmp: s = "cmp: %e0%0 - %e1%1"; break;
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case RLO_mov: s = "mov: %e0%0 = %e1%1"; break;
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case RLO_or: s = "or: %e0%0 |= %e1%1"; break;
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case RLO_rol: s = "rol: %e0%0 <<= %e1%1"; break;
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case RLO_rolc: s = "rol: %e0%0 <<= %e1%1,CY"; break;
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case RLO_ror: s = "ror: %e0%0 >>= %e1%1"; break;
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case RLO_rorc: s = "ror: %e0%0 >>= %e1%1,CY"; break;
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case RLO_sar: s = "sar: %e0%0 >>= %e1%1 signed"; break;
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case RLO_sel: s = "sel: rb = %1"; break;
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case RLO_shr: s = "shr: %e0%0 >>= %e1%1 unsigned"; break;
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case RLO_shl: s = "shl: %e0%0 <<= %e1%1"; break;
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case RLO_skip: s = "skip: if %c1"; break;
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case RLO_sub: s = "sub: %e0%0 -= %e1%1"; break;
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case RLO_subc: s = "subc: %e0%0 -= %e1%1 - CY"; break;
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case RLO_xch: s = "xch: %e0%0 <-> %e1%1"; break;
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case RLO_xor: s = "xor: %e0%0 ^= %e1%1"; break;
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}
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sprintf(buf, "%s%%W%%f\t\033[32m%s\033[0m", s, opcode.syntax);
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s = buf;
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#endif
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for (; *s; s++)
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{
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if (*s != '%')
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{
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PC (*s);
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}
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else
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{
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RL78_Opcode_Operand * oper;
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int do_hex = 0;
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int do_addr = 0;
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int do_es = 0;
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int do_sfr = 0;
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int do_cond = 0;
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int do_bang = 0;
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while (1)
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{
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s ++;
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switch (*s)
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{
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case 'x':
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do_hex = 1;
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break;
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case '!':
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do_bang = 1;
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break;
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case 'e':
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do_es = 1;
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break;
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case 'a':
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do_addr = 1;
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break;
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case 's':
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do_sfr = 1;
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break;
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case 'c':
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do_cond = 1;
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break;
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default:
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goto no_more_modifiers;
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}
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}
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no_more_modifiers:;
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switch (*s)
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{
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case '%':
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PC ('%');
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break;
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#if DEBUG_SEMANTICS
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case 'W':
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if (opcode.size == RL78_Word)
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PR (PS, " \033[33mW\033[0m");
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break;
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case 'f':
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if (opcode.flags)
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{
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char *comma = "";
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PR (PS, " \033[35m");
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if (opcode.flags & RL78_PSW_Z)
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{ PR (PS, "Z"); comma = ","; }
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if (opcode.flags & RL78_PSW_AC)
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{ PR (PS, "%sAC", comma); comma = ","; }
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if (opcode.flags & RL78_PSW_CY)
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{ PR (PS, "%sCY", comma); comma = ","; }
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PR (PS, "\033[0m");
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}
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break;
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#endif
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case '0':
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case '1':
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oper = *s == '0' ? &opcode.op[0] : &opcode.op[1];
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if (do_es)
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{
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if (oper->use_es && indirect_type (oper->type))
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PR (PS, "es:");
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}
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if (do_bang)
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{
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/* If we are going to display SP by name, we must omit the bang. */
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if ((oper->type == RL78_Operand_Indirect
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|| oper->type == RL78_Operand_BitIndirect)
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&& oper->reg == RL78_Reg_None
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&& do_sfr
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&& ((oper->addend == 0xffff8 && opcode.size == RL78_Word)
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|| (oper->addend == 0x0fff8 && do_es && opcode.size == RL78_Word)))
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;
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else
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PC ('!');
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}
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if (do_cond)
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{
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PR (PS, "%s", condition_names[oper->condition]);
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break;
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}
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switch (oper->type)
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{
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case RL78_Operand_Immediate:
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if (do_addr)
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dis->print_address_func (oper->addend, dis);
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else if (do_hex
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|| oper->addend > 999
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|| oper->addend < -999)
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PR (PS, "%#x", oper->addend);
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else
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PR (PS, "%d", oper->addend);
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break;
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case RL78_Operand_Register:
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PR (PS, "%s", register_names[oper->reg]);
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break;
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case RL78_Operand_Bit:
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PR (PS, "%s.%d", register_names[oper->reg], oper->bit_number);
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break;
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case RL78_Operand_Indirect:
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case RL78_Operand_BitIndirect:
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switch (oper->reg)
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{
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case RL78_Reg_None:
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if (oper->addend == 0xffffa && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "psw");
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else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Word)
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PR (PS, "sp");
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else if (oper->addend == 0x0fff8 && do_sfr && do_es && opcode.size == RL78_Word)
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PR (PS, "sp");
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else if (oper->addend == 0xffff8 && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "spl");
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else if (oper->addend == 0xffff9 && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "sph");
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else if (oper->addend == 0xffffc && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "cs");
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else if (oper->addend == 0xffffd && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "es");
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else if (oper->addend == 0xffffe && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "pmc");
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else if (oper->addend == 0xfffff && do_sfr && opcode.size == RL78_Byte)
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PR (PS, "mem");
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else if (oper->addend >= 0xffe20)
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PR (PS, "%#x", oper->addend);
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else
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{
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int faddr = oper->addend;
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if (do_es && ! oper->use_es)
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faddr += 0xf0000;
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dis->print_address_func (faddr, dis);
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}
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break;
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case RL78_Reg_B:
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case RL78_Reg_C:
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case RL78_Reg_BC:
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PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
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break;
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default:
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PR (PS, "[%s", register_names[oper->reg]);
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if (oper->reg2 != RL78_Reg_None)
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PR (PS, "+%s", register_names[oper->reg2]);
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if (oper->addend || do_addr)
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PR (PS, "+%d", oper->addend);
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PC (']');
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break;
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}
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if (oper->type == RL78_Operand_BitIndirect)
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PR (PS, ".%d", oper->bit_number);
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break;
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#if DEBUG_SEMANTICS
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/* Shouldn't happen - push and pop don't print
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[SP] directly. But we *do* use them for
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semantic debugging. */
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case RL78_Operand_PostInc:
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PR (PS, "[%s++]", register_names[oper->reg]);
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break;
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case RL78_Operand_PreDec:
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PR (PS, "[--%s]", register_names[oper->reg]);
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break;
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#endif
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default:
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/* If we ever print this, that means the
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programmer tried to print an operand with a
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type we don't expect. Print the line and
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operand number from rl78-decode.opc for
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them. */
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PR (PS, "???%d.%d", opcode.lineno, *s - '0');
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break;
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}
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}
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}
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}
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#if DEBUG_SEMANTICS
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PR (PS, "\t\033[34m(line %d)\033[0m", opcode.lineno);
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#endif
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return rv;
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}
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int
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print_insn_rl78 (bfd_vma addr, disassemble_info * dis)
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{
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return print_insn_rl78_common (addr, dis, RL78_ISA_DEFAULT);
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}
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int
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print_insn_rl78_g10 (bfd_vma addr, disassemble_info * dis)
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{
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return print_insn_rl78_common (addr, dis, RL78_ISA_G10);
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}
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int
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print_insn_rl78_g13 (bfd_vma addr, disassemble_info * dis)
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{
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return print_insn_rl78_common (addr, dis, RL78_ISA_G13);
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}
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int
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print_insn_rl78_g14 (bfd_vma addr, disassemble_info * dis)
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{
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return print_insn_rl78_common (addr, dis, RL78_ISA_G14);
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}
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disassembler_ftype
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rl78_get_disassembler (bfd *abfd)
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{
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int cpu = E_FLAG_RL78_ANY_CPU;
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if (abfd != NULL && bfd_get_flavour (abfd) == bfd_target_elf_flavour)
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cpu = abfd->tdata.elf_obj_data->elf_header->e_flags & E_FLAG_RL78_CPU_MASK;
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switch (cpu)
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{
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case E_FLAG_RL78_G10:
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return print_insn_rl78_g10;
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case E_FLAG_RL78_G13:
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return print_insn_rl78_g13;
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case E_FLAG_RL78_G14:
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return print_insn_rl78_g14;
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default:
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return print_insn_rl78;
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}
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}
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