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c524b5f2f6
I was looking for cases where a GCC patch under evaluation would cause test results to change. Quite surprisingly the mcore-elf port showed test differences. After a fair amount of digging my conclusion was the sequences before/after the patch should have been semantically the same. Of course if the code is supposed to behave the same, then that points to problems elsewhere (assembler, linker, simulator). Sure enough the mcore simulator was mis-handling the sign extension instructions. The simulator implementation of sextb is via paired shift-by-24 operations. Similarly the simulator implements sexth via paired shift-by-16 operations. The temporary holding the value was declared as a "long" thus this approach worked fine for hosts with a 32 bit wide long and failed miserably for hosts with a 64 bit wide long. This patch makes the shift count automatically adjust based on the size of the temporary. It includes a simple test for sextb and sexth. I have _not_ done a full audit of the mcore simulator for more 32->64 bit issues. This also fixes 443 execution tests in the GCC testsuite |
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| aarch64 | ||
| arm | ||
| avr | ||
| bfin | ||
| bpf | ||
| common | ||
| config | ||
| cr16 | ||
| cris | ||
| d10v | ||
| example-synacor | ||
| frv | ||
| ft32 | ||
| h8300 | ||
| iq2000 | ||
| lib | ||
| lm32 | ||
| m32c | ||
| m32r | ||
| m68hc11 | ||
| mcore | ||
| microblaze | ||
| mips | ||
| mn10300 | ||
| moxie | ||
| msp430 | ||
| or1k | ||
| pru | ||
| riscv | ||
| sh | ||
| v850 | ||
| .gitignore | ||
| ChangeLog-2021 | ||
| local.mk | ||