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c1e679ec0a
2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (process_drex): Delete. Remove SSE5 support. (build_modrm_byte): Remove DREX handling support. (DREX_*): Delete. (drex_byte): Delete. (md_assemble): Remove DREX handling support. (process_operands): Remove DREX, SSE5 support. (i386_insn): Remove DREX. <gas/testsuite changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Remove SSE5 tests. * gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests. * gas/i386/x86-64-sse5.d: Ditto. * gas/i386/arch-10-1.l: Remove SSE5 tests. * gas/i386/arch-10-2.l: Ditto. * gas/i386/arch-10-3.l: Ditto. * gas/i386/arch-10-4.l: Ditto. * gas/i386/arch-10.d: Ditto. * gas/i386/arch-10.s: Ditto. * gas/i386/arch-4.s: Delete. Remove SSE5 tests. * gas/i386/arch-4.d: Ditto. * gas/i386/arch-8.s: Ditto. * gas/i386/arch-8.d: Ditto. * gas/i386/arch-2.s: Remove SSE5 tests. * gas/i386/arch-2.d: Remove SSE5 tests. * gas/i386/x86-64-arch-2.s: Ditto. <opcodes changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (Cpusse5): Delete. (i386_cpu_flags): Delete. * i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc. * i386-opc.tbl: Remove SSE5 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling. (print_drex_arg): Delete. (OP_DREX4): Delete. (OP_DREX3): Delete. (OP_DREX_ICMP): Delete. (OP_DREX_FCMP): Delete. (DREX_*): Delete. (THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.
594 lines
18 KiB
C
594 lines
18 KiB
C
/* Declarations for Intel 80386 opcode table
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Copyright 2007, 2008, 2009
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Free Software Foundation, Inc.
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS; see the file COPYING. If not, write to the Free
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Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "opcode/i386.h"
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#ifdef HAVE_LIMITS_H
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#include <limits.h>
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#endif
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#ifndef CHAR_BIT
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#define CHAR_BIT 8
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#endif
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/* Position of cpu flags bitfiled. */
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/* i186 or better required */
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#define Cpu186 0
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/* i286 or better required */
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#define Cpu286 (Cpu186 + 1)
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/* i386 or better required */
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#define Cpu386 (Cpu286 + 1)
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/* i486 or better required */
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#define Cpu486 (Cpu386 + 1)
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/* i585 or better required */
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#define Cpu586 (Cpu486 + 1)
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/* i686 or better required */
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#define Cpu686 (Cpu586 + 1)
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/* CLFLUSH Instuction support required */
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#define CpuClflush (Cpu686 + 1)
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/* SYSCALL Instuctions support required */
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#define CpuSYSCALL (CpuClflush + 1)
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/* MMX support required */
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#define CpuMMX (CpuSYSCALL + 1)
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/* SSE support required */
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#define CpuSSE (CpuMMX + 1)
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/* SSE2 support required */
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#define CpuSSE2 (CpuSSE + 1)
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/* 3dnow! support required */
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#define Cpu3dnow (CpuSSE2 + 1)
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/* 3dnow! Extensions support required */
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#define Cpu3dnowA (Cpu3dnow + 1)
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/* SSE3 support required */
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#define CpuSSE3 (Cpu3dnowA + 1)
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/* VIA PadLock required */
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#define CpuPadLock (CpuSSE3 + 1)
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/* AMD Secure Virtual Machine Ext-s required */
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#define CpuSVME (CpuPadLock + 1)
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/* VMX Instructions required */
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#define CpuVMX (CpuSVME + 1)
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/* SMX Instructions required */
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#define CpuSMX (CpuVMX + 1)
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/* SSSE3 support required */
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#define CpuSSSE3 (CpuSMX + 1)
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/* SSE4a support required */
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#define CpuSSE4a (CpuSSSE3 + 1)
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/* ABM New Instructions required */
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#define CpuABM (CpuSSE4a + 1)
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/* SSE4.1 support required */
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#define CpuSSE4_1 (CpuABM + 1)
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/* SSE4.2 support required */
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#define CpuSSE4_2 (CpuSSE4_1 + 1)
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/* AVX support required */
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#define CpuAVX (CpuSSE4_2 + 1)
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/* Xsave/xrstor New Instuctions support required */
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#define CpuXsave (CpuAVX + 1)
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/* AES support required */
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#define CpuAES (CpuXsave + 1)
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/* PCLMUL support required */
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#define CpuPCLMUL (CpuAES + 1)
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/* FMA support required */
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#define CpuFMA (CpuPCLMUL + 1)
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/* MOVBE Instuction support required */
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#define CpuMovbe (CpuFMA + 1)
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/* EPT Instructions required */
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#define CpuEPT (CpuMovbe + 1)
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/* RDTSCP Instuction support required */
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#define CpuRdtscp (CpuEPT + 1)
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/* 64bit support available, used by -march= in assembler. */
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#define CpuLM (CpuRdtscp + 1)
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/* 64bit support required */
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#define Cpu64 (CpuLM + 1)
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/* Not supported in the 64bit mode */
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#define CpuNo64 (Cpu64 + 1)
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/* The last bitfield in i386_cpu_flags. */
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#define CpuMax CpuNo64
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#define CpuNumOfUints \
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(CpuMax / sizeof (unsigned int) / CHAR_BIT + 1)
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#define CpuNumOfBits \
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(CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT)
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/* If you get a compiler error for zero width of the unused field,
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comment it out. */
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#define CpuUnused (CpuMax + 1)
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/* We can check if an instruction is available with array instead
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of bitfield. */
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typedef union i386_cpu_flags
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{
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struct
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{
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unsigned int cpui186:1;
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unsigned int cpui286:1;
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unsigned int cpui386:1;
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unsigned int cpui486:1;
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unsigned int cpui586:1;
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unsigned int cpui686:1;
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unsigned int cpuclflush:1;
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unsigned int cpusyscall:1;
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unsigned int cpummx:1;
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unsigned int cpusse:1;
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unsigned int cpusse2:1;
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unsigned int cpua3dnow:1;
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unsigned int cpua3dnowa:1;
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unsigned int cpusse3:1;
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unsigned int cpupadlock:1;
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unsigned int cpusvme:1;
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unsigned int cpuvmx:1;
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unsigned int cpusmx:1;
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unsigned int cpussse3:1;
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unsigned int cpusse4a:1;
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unsigned int cpuabm:1;
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unsigned int cpusse4_1:1;
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unsigned int cpusse4_2:1;
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unsigned int cpuavx:1;
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unsigned int cpuxsave:1;
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unsigned int cpuaes:1;
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unsigned int cpupclmul:1;
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unsigned int cpufma:1;
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unsigned int cpumovbe:1;
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unsigned int cpuept:1;
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unsigned int cpurdtscp:1;
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unsigned int cpulm:1;
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unsigned int cpu64:1;
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unsigned int cpuno64:1;
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#ifdef CpuUnused
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unsigned int unused:(CpuNumOfBits - CpuUnused);
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#endif
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} bitfield;
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unsigned int array[CpuNumOfUints];
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} i386_cpu_flags;
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/* Position of opcode_modifier bits. */
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/* has direction bit. */
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#define D 0
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/* set if operands can be words or dwords encoded the canonical way */
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#define W (D + 1)
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/* Skip the current insn and use the next insn in i386-opc.tbl to swap
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operand in encoding. */
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#define S (W + 1)
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/* insn has a modrm byte. */
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#define Modrm (S + 1)
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/* register is in low 3 bits of opcode */
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#define ShortForm (Modrm + 1)
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/* special case for jump insns. */
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#define Jump (ShortForm + 1)
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/* call and jump */
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#define JumpDword (Jump + 1)
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/* loop and jecxz */
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#define JumpByte (JumpDword + 1)
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/* special case for intersegment leaps/calls */
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#define JumpInterSegment (JumpByte + 1)
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/* FP insn memory format bit, sized by 0x4 */
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#define FloatMF (JumpInterSegment + 1)
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/* src/dest swap for floats. */
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#define FloatR (FloatMF + 1)
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/* has float insn direction bit. */
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#define FloatD (FloatR + 1)
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/* needs size prefix if in 32-bit mode */
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#define Size16 (FloatD + 1)
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/* needs size prefix if in 16-bit mode */
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#define Size32 (Size16 + 1)
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/* needs size prefix if in 64-bit mode */
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#define Size64 (Size32 + 1)
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/* instruction ignores operand size prefix and in Intel mode ignores
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mnemonic size suffix check. */
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#define IgnoreSize (Size64 + 1)
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/* default insn size depends on mode */
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#define DefaultSize (IgnoreSize + 1)
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/* b suffix on instruction illegal */
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#define No_bSuf (DefaultSize + 1)
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/* w suffix on instruction illegal */
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#define No_wSuf (No_bSuf + 1)
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/* l suffix on instruction illegal */
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#define No_lSuf (No_wSuf + 1)
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/* s suffix on instruction illegal */
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#define No_sSuf (No_lSuf + 1)
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/* q suffix on instruction illegal */
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#define No_qSuf (No_sSuf + 1)
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/* long double suffix on instruction illegal */
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#define No_ldSuf (No_qSuf + 1)
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/* instruction needs FWAIT */
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#define FWait (No_ldSuf + 1)
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/* quick test for string instructions */
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#define IsString (FWait + 1)
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/* fake an extra reg operand for clr, imul and special register
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processing for some instructions. */
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#define RegKludge (IsString + 1)
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/* The first operand must be xmm0 */
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#define FirstXmm0 (RegKludge + 1)
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/* An implicit xmm0 as the first operand */
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#define Implicit1stXmm0 (FirstXmm0 + 1)
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/* BYTE is OK in Intel syntax. */
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#define ByteOkIntel (Implicit1stXmm0 + 1)
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/* Convert to DWORD */
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#define ToDword (ByteOkIntel + 1)
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/* Convert to QWORD */
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#define ToQword (ToDword + 1)
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/* Address prefix changes operand 0 */
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#define AddrPrefixOp0 (ToQword + 1)
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/* opcode is a prefix */
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#define IsPrefix (AddrPrefixOp0 + 1)
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/* instruction has extension in 8 bit imm */
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#define ImmExt (IsPrefix + 1)
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/* instruction don't need Rex64 prefix. */
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#define NoRex64 (ImmExt + 1)
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/* instruction require Rex64 prefix. */
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#define Rex64 (NoRex64 + 1)
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/* deprecated fp insn, gets a warning */
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#define Ugh (Rex64 + 1)
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/* insn has VEX prefix. */
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#define Vex (Ugh + 1)
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/* insn has 256bit VEX prefix. */
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#define Vex256 (Vex + 1)
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/* insn has VEX NDS. Register-only source is encoded in Vex prefix.
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We use VexNDS on insns with VEX DDS since the register-only source
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is the second source register. */
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#define VexNDS (Vex256 + 1)
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/* insn has VEX NDD. Register destination is encoded in Vex
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prefix. */
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#define VexNDD (VexNDS + 1)
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/* insn has VEX W0. */
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#define VexW0 (VexNDD + 1)
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/* insn has VEX W1. */
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#define VexW1 (VexW0 + 1)
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/* insn has VEX 0x0F opcode prefix. */
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#define Vex0F (VexW1 + 1)
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/* insn has VEX 0x0F38 opcode prefix. */
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#define Vex0F38 (Vex0F + 1)
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/* insn has VEX 0x0F3A opcode prefix. */
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#define Vex0F3A (Vex0F38 + 1)
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/* insn has VEX prefix with 3 soures. */
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#define Vex3Sources (Vex0F3A + 1)
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/* instruction has VEX 8 bit imm */
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#define VexImmExt (Vex3Sources + 1)
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/* SSE to AVX support required */
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#define SSE2AVX (VexImmExt + 1)
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/* No AVX equivalent */
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#define NoAVX (SSE2AVX + 1)
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/* Compatible with old (<= 2.8.1) versions of gcc */
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#define OldGcc (NoAVX + 1)
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/* AT&T mnemonic. */
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#define ATTMnemonic (OldGcc + 1)
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/* AT&T syntax. */
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#define ATTSyntax (ATTMnemonic + 1)
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/* Intel syntax. */
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#define IntelSyntax (ATTSyntax + 1)
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/* The last bitfield in i386_opcode_modifier. */
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#define Opcode_Modifier_Max IntelSyntax
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typedef struct i386_opcode_modifier
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{
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unsigned int d:1;
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unsigned int w:1;
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unsigned int s:1;
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unsigned int modrm:1;
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unsigned int shortform:1;
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unsigned int jump:1;
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unsigned int jumpdword:1;
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unsigned int jumpbyte:1;
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unsigned int jumpintersegment:1;
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unsigned int floatmf:1;
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unsigned int floatr:1;
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unsigned int floatd:1;
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unsigned int size16:1;
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unsigned int size32:1;
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unsigned int size64:1;
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unsigned int ignoresize:1;
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unsigned int defaultsize:1;
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unsigned int no_bsuf:1;
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unsigned int no_wsuf:1;
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unsigned int no_lsuf:1;
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unsigned int no_ssuf:1;
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unsigned int no_qsuf:1;
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unsigned int no_ldsuf:1;
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unsigned int fwait:1;
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unsigned int isstring:1;
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unsigned int regkludge:1;
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unsigned int firstxmm0:1;
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unsigned int implicit1stxmm0:1;
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unsigned int byteokintel:1;
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unsigned int todword:1;
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unsigned int toqword:1;
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unsigned int addrprefixop0:1;
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unsigned int isprefix:1;
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unsigned int immext:1;
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unsigned int norex64:1;
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unsigned int rex64:1;
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unsigned int ugh:1;
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unsigned int vex:1;
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unsigned int vex256:1;
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unsigned int vexnds:1;
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unsigned int vexndd:1;
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unsigned int vexw0:1;
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unsigned int vexw1:1;
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unsigned int vex0f:1;
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unsigned int vex0f38:1;
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unsigned int vex0f3a:1;
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unsigned int vex3sources:1;
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unsigned int veximmext:1;
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unsigned int sse2avx:1;
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unsigned int noavx:1;
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unsigned int oldgcc:1;
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unsigned int attmnemonic:1;
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unsigned int attsyntax:1;
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unsigned int intelsyntax:1;
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} i386_opcode_modifier;
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/* Position of operand_type bits. */
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/* 8bit register */
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#define Reg8 0
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/* 16bit register */
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#define Reg16 (Reg8 + 1)
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/* 32bit register */
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#define Reg32 (Reg16 + 1)
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/* 64bit register */
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#define Reg64 (Reg32 + 1)
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/* Floating pointer stack register */
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#define FloatReg (Reg64 + 1)
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/* MMX register */
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#define RegMMX (FloatReg + 1)
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/* SSE register */
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#define RegXMM (RegMMX + 1)
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/* AVX registers */
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#define RegYMM (RegXMM + 1)
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/* Control register */
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#define Control (RegYMM + 1)
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/* Debug register */
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#define Debug (Control + 1)
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/* Test register */
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#define Test (Debug + 1)
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/* 2 bit segment register */
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#define SReg2 (Test + 1)
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/* 3 bit segment register */
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#define SReg3 (SReg2 + 1)
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/* 1 bit immediate */
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#define Imm1 (SReg3 + 1)
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/* 8 bit immediate */
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#define Imm8 (Imm1 + 1)
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/* 8 bit immediate sign extended */
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#define Imm8S (Imm8 + 1)
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/* 16 bit immediate */
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#define Imm16 (Imm8S + 1)
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/* 32 bit immediate */
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#define Imm32 (Imm16 + 1)
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/* 32 bit immediate sign extended */
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#define Imm32S (Imm32 + 1)
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/* 64 bit immediate */
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#define Imm64 (Imm32S + 1)
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/* 8bit/16bit/32bit displacements are used in different ways,
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depending on the instruction. For jumps, they specify the
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size of the PC relative displacement, for instructions with
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memory operand, they specify the size of the offset relative
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to the base register, and for instructions with memory offset
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such as `mov 1234,%al' they specify the size of the offset
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relative to the segment base. */
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/* 8 bit displacement */
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#define Disp8 (Imm64 + 1)
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/* 16 bit displacement */
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#define Disp16 (Disp8 + 1)
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/* 32 bit displacement */
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#define Disp32 (Disp16 + 1)
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/* 32 bit signed displacement */
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#define Disp32S (Disp32 + 1)
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/* 64 bit displacement */
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#define Disp64 (Disp32S + 1)
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/* Accumulator %al/%ax/%eax/%rax */
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#define Acc (Disp64 + 1)
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/* Floating pointer top stack register %st(0) */
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#define FloatAcc (Acc + 1)
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/* Register which can be used for base or index in memory operand. */
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#define BaseIndex (FloatAcc + 1)
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/* Register to hold in/out port addr = dx */
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#define InOutPortReg (BaseIndex + 1)
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/* Register to hold shift count = cl */
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#define ShiftCount (InOutPortReg + 1)
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/* Absolute address for jump. */
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#define JumpAbsolute (ShiftCount + 1)
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/* String insn operand with fixed es segment */
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#define EsSeg (JumpAbsolute + 1)
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/* RegMem is for instructions with a modrm byte where the register
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destination operand should be encoded in the mod and regmem fields.
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Normally, it will be encoded in the reg field. We add a RegMem
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flag to the destination register operand to indicate that it should
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be encoded in the regmem field. */
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#define RegMem (EsSeg + 1)
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/* Memory. */
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#define Mem (RegMem + 1)
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/* BYTE memory. */
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#define Byte (Mem + 1)
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/* WORD memory. 2 byte */
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#define Word (Byte + 1)
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/* DWORD memory. 4 byte */
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#define Dword (Word + 1)
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/* FWORD memory. 6 byte */
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#define Fword (Dword + 1)
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/* QWORD memory. 8 byte */
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#define Qword (Fword + 1)
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/* TBYTE memory. 10 byte */
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#define Tbyte (Qword + 1)
|
|
/* XMMWORD memory. */
|
|
#define Xmmword (Tbyte + 1)
|
|
/* YMMWORD memory. */
|
|
#define Ymmword (Xmmword + 1)
|
|
/* Unspecified memory size. */
|
|
#define Unspecified (Ymmword + 1)
|
|
/* Any memory size. */
|
|
#define Anysize (Unspecified + 1)
|
|
|
|
/* The last bitfield in i386_operand_type. */
|
|
#define OTMax Anysize
|
|
|
|
#define OTNumOfUints \
|
|
(OTMax / sizeof (unsigned int) / CHAR_BIT + 1)
|
|
#define OTNumOfBits \
|
|
(OTNumOfUints * sizeof (unsigned int) * CHAR_BIT)
|
|
|
|
/* If you get a compiler error for zero width of the unused field,
|
|
comment it out. */
|
|
#define OTUnused (OTMax + 1)
|
|
|
|
typedef union i386_operand_type
|
|
{
|
|
struct
|
|
{
|
|
unsigned int reg8:1;
|
|
unsigned int reg16:1;
|
|
unsigned int reg32:1;
|
|
unsigned int reg64:1;
|
|
unsigned int floatreg:1;
|
|
unsigned int regmmx:1;
|
|
unsigned int regxmm:1;
|
|
unsigned int regymm:1;
|
|
unsigned int control:1;
|
|
unsigned int debug:1;
|
|
unsigned int test:1;
|
|
unsigned int sreg2:1;
|
|
unsigned int sreg3:1;
|
|
unsigned int imm1:1;
|
|
unsigned int imm8:1;
|
|
unsigned int imm8s:1;
|
|
unsigned int imm16:1;
|
|
unsigned int imm32:1;
|
|
unsigned int imm32s:1;
|
|
unsigned int imm64:1;
|
|
unsigned int disp8:1;
|
|
unsigned int disp16:1;
|
|
unsigned int disp32:1;
|
|
unsigned int disp32s:1;
|
|
unsigned int disp64:1;
|
|
unsigned int acc:1;
|
|
unsigned int floatacc:1;
|
|
unsigned int baseindex:1;
|
|
unsigned int inoutportreg:1;
|
|
unsigned int shiftcount:1;
|
|
unsigned int jumpabsolute:1;
|
|
unsigned int esseg:1;
|
|
unsigned int regmem:1;
|
|
unsigned int mem:1;
|
|
unsigned int byte:1;
|
|
unsigned int word:1;
|
|
unsigned int dword:1;
|
|
unsigned int fword:1;
|
|
unsigned int qword:1;
|
|
unsigned int tbyte:1;
|
|
unsigned int xmmword:1;
|
|
unsigned int ymmword:1;
|
|
unsigned int unspecified:1;
|
|
unsigned int anysize:1;
|
|
#ifdef OTUnused
|
|
unsigned int unused:(OTNumOfBits - OTUnused);
|
|
#endif
|
|
} bitfield;
|
|
unsigned int array[OTNumOfUints];
|
|
} i386_operand_type;
|
|
|
|
typedef struct template
|
|
{
|
|
/* instruction name sans width suffix ("mov" for movl insns) */
|
|
char *name;
|
|
|
|
/* how many operands */
|
|
unsigned int operands;
|
|
|
|
/* base_opcode is the fundamental opcode byte without optional
|
|
prefix(es). */
|
|
unsigned int base_opcode;
|
|
#define Opcode_D 0x2 /* Direction bit:
|
|
set if Reg --> Regmem;
|
|
unset if Regmem --> Reg. */
|
|
#define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */
|
|
#define Opcode_FloatD 0x400 /* Direction bit for float insns. */
|
|
|
|
/* extension_opcode is the 3 bit extension for group <n> insns.
|
|
This field is also used to store the 8-bit opcode suffix for the
|
|
AMD 3DNow! instructions.
|
|
If this template has no extension opcode (the usual case) use None
|
|
Instructions */
|
|
unsigned int extension_opcode;
|
|
#define None 0xffff /* If no extension_opcode is possible. */
|
|
|
|
/* Opcode length. */
|
|
unsigned char opcode_length;
|
|
|
|
/* cpu feature flags */
|
|
i386_cpu_flags cpu_flags;
|
|
|
|
/* the bits in opcode_modifier are used to generate the final opcode from
|
|
the base_opcode. These bits also are used to detect alternate forms of
|
|
the same instruction */
|
|
i386_opcode_modifier opcode_modifier;
|
|
|
|
/* operand_types[i] describes the type of operand i. This is made
|
|
by OR'ing together all of the possible type masks. (e.g.
|
|
'operand_types[i] = Reg|Imm' specifies that operand i can be
|
|
either a register or an immediate operand. */
|
|
i386_operand_type operand_types[MAX_OPERANDS];
|
|
}
|
|
template;
|
|
|
|
extern const template i386_optab[];
|
|
|
|
/* these are for register name --> number & type hash lookup */
|
|
typedef struct
|
|
{
|
|
char *reg_name;
|
|
i386_operand_type reg_type;
|
|
unsigned char reg_flags;
|
|
#define RegRex 0x1 /* Extended register. */
|
|
#define RegRex64 0x2 /* Extended 8 bit register. */
|
|
unsigned char reg_num;
|
|
#define RegRip ((unsigned char ) ~0)
|
|
#define RegEip (RegRip - 1)
|
|
/* EIZ and RIZ are fake index registers. */
|
|
#define RegEiz (RegEip - 1)
|
|
#define RegRiz (RegEiz - 1)
|
|
/* FLAT is a fake segment register (Intel mode). */
|
|
#define RegFlat ((unsigned char) ~0)
|
|
signed char dw2_regnum[2];
|
|
#define Dw2Inval (-1)
|
|
}
|
|
reg_entry;
|
|
|
|
/* Entries in i386_regtab. */
|
|
#define REGNAM_AL 1
|
|
#define REGNAM_AX 25
|
|
#define REGNAM_EAX 41
|
|
|
|
extern const reg_entry i386_regtab[];
|
|
extern const unsigned int i386_regtab_size;
|
|
|
|
typedef struct
|
|
{
|
|
char *seg_name;
|
|
unsigned int seg_prefix;
|
|
}
|
|
seg_entry;
|
|
|
|
extern const seg_entry cs;
|
|
extern const seg_entry ds;
|
|
extern const seg_entry ss;
|
|
extern const seg_entry es;
|
|
extern const seg_entry fs;
|
|
extern const seg_entry gs;
|