..
acinclude.m4
sim: punt x86-specific bswap logic
2016-01-04 05:04:30 -05:00
aclocal.m4
Regenerate sim/common/aclocal.m4 and sim/common/configure...
2015-01-07 14:00:06 +04:00
callback.c
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
cgen-accfp.c
common/
2010-01-25 04:08:52 +00:00
cgen-cpu.h
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
cgen-defs.h
sim: delete dead current_state globals
2016-01-02 10:27:56 -05:00
cgen-engine.h
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2016-01-01 08:43:22 +04:00
cgen-fpu.c
cgen-fpu.h
common/
2010-01-25 04:08:52 +00:00
cgen-mem.h
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
cgen-ops.h
sim: convert to bfd_endian
2016-01-03 00:18:07 -05:00
cgen-par.c
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cgen-par.h
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cgen-run.c
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cgen-scache.c
sim: unify min/max macros
2016-01-04 22:24:03 -05:00
cgen-scache.h
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
cgen-sim.h
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2016-01-01 08:43:22 +04:00
cgen-trace.c
sim: unify min/max macros
2016-01-04 22:24:03 -05:00
cgen-trace.h
GDB copyright headers update after running GDB's copyright.py script.
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cgen-types.h
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2016-01-01 08:43:22 +04:00
cgen-utils.c
sim: unify min/max macros
2016-01-04 22:24:03 -05:00
cgen.sh
sim: gennltvals.sh: handle split out newlib source tree
2015-04-21 03:10:16 -04:00
ChangeLog
sim: trace: add support for disassembling
2016-01-05 14:28:37 -05:00
config.in
sim: drop host endian configure option
2016-01-03 00:52:51 -05:00
configure
sim: punt x86-specific bswap logic
2016-01-04 05:04:30 -05:00
configure.ac
sim: dv-cfi: check for posix_fallocate
2011-11-07 16:28:52 +00:00
dv-cfi.c
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
dv-cfi.h
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dv-core.c
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dv-glue.c
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dv-pal.c
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dv-sockser.c
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dv-sockser.h
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2016-01-01 08:43:22 +04:00
gdbinit.in
* aclocal.m4 (SIM_AC_OUTPUT): Substitute @cgen_breaks@ for "break
2004-12-07 23:37:35 +00:00
genmloop.sh
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2016-01-01 08:43:22 +04:00
gennltvals.sh
sim: mcore: switch to common syscall handling
2015-04-21 03:10:16 -04:00
gentmap.c
sim: callback: add human readable strings for debugging to maps
2015-06-17 13:19:51 -04:00
gentvals.sh
sim: gennltvals.sh: handle split out newlib source tree
2015-04-21 03:10:16 -04:00
hw-alloc.c
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2016-01-01 08:43:22 +04:00
hw-alloc.h
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hw-base.c
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hw-base.h
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hw-device.c
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2016-01-01 08:43:22 +04:00
hw-device.h
sim: clean up some more device detritus
2016-01-03 04:23:10 -05:00
hw-events.c
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2016-01-01 08:43:22 +04:00
hw-events.h
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hw-handles.c
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hw-handles.h
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hw-instances.c
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hw-instances.h
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hw-main.h
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hw-ports.c
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hw-ports.h
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hw-properties.c
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hw-properties.h
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hw-tree.c
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hw-tree.h
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Make-common.in
sim: punt x86-specific bswap logic
2016-01-04 05:04:30 -05:00
Makefile.in
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2016-01-01 08:43:22 +04:00
nltvals.def
sim: mcore: switch to common syscall handling
2015-04-21 03:10:16 -04:00
nrun.c
sim: nrun: use lbasename
2016-01-03 03:50:08 -05:00
run.1
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sim-abort.c
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sim-alu.h
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sim-arange.c
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sim-arange.h
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sim-assert.h
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2016-01-01 08:43:22 +04:00
sim-base.h
sim: delete dead current_state globals
2016-01-02 10:27:56 -05:00
sim-basics.h
sim: unify min/max macros
2016-01-04 22:24:03 -05:00
sim-bits.c
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2016-01-01 08:43:22 +04:00
sim-bits.h
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sim-close.c
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sim-command.c
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2016-01-01 08:43:22 +04:00
sim-config.c
sim: drop host endian configure option
2016-01-03 00:52:51 -05:00
sim-config.h
sim: punt x86-specific bswap logic
2016-01-04 05:04:30 -05:00
sim-core.c
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
sim-core.h
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sim-cpu.c
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2016-01-01 08:43:22 +04:00
sim-cpu.h
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2016-01-01 08:43:22 +04:00
sim-endian.c
sim: drop host endian configure option
2016-01-03 00:52:51 -05:00
sim-endian.h
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
sim-engine.c
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2016-01-01 08:43:22 +04:00
sim-engine.h
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2016-01-01 08:43:22 +04:00
sim-events.c
sim: convert to bfd_endian
2016-01-03 00:18:07 -05:00
sim-events.h
sim: convert to bfd_endian
2016-01-03 00:18:07 -05:00
sim-fpu.c
GDB copyright headers update after running GDB's copyright.py script.
2016-01-01 08:43:22 +04:00
sim-fpu.h
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sim-hload.c
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sim-hrw.c
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sim-hw.c
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sim-hw.h
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sim-info.c
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sim-inline.c
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sim-inline.h
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sim-io.c
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sim-io.h
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sim-load.c
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sim-memopt.c
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sim-memopt.h
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sim-model.c
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sim-model.h
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sim-module.c
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sim-module.h
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sim-n-bits.h
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2016-01-01 08:43:22 +04:00
sim-n-core.h
sim: drop host endian configure option
2016-01-03 00:52:51 -05:00
sim-n-endian.h
sim: drop host endian configure option
2016-01-03 00:52:51 -05:00
sim-options.c
sim: parse_args: polish getopt error message
2016-01-04 05:08:26 -05:00
sim-options.h
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sim-profile.c
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sim-profile.h
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sim-reason.c
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sim-reg.c
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sim-resume.c
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sim-run.c
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sim-signal.c
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sim-signal.h
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sim-stop.c
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sim-syscall.c
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sim-syscall.h
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sim-trace.c
sim: trace: add support for disassembling
2016-01-05 14:28:37 -05:00
sim-trace.h
sim: trace: add support for disassembling
2016-01-05 14:28:37 -05:00
sim-types.h
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2016-01-01 08:43:22 +04:00
sim-utils.c
sim: use STATE_MAGIC helper
2016-01-04 23:01:14 -05:00
sim-utils.h
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sim-watch.c
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sim-watch.h
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syscall.c
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version.h
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