Jaydeep Patil 1c37b30945 sim/riscv: fix JALR instruction simulation ... Fix 32bit 'jalr rd,ra,imm' integer instruction, where RD was written before using it to calculate destination address. This commit also improves testutils.inc for riscv; make use of pushsection and popsection when adding things to .data, and setup the %gp global pointer register within the 'start' macro. Approved-By: Andrew Burgess <aburgess@redhat.com>		2023-10-18 17:55:31 +01:00
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acinclude.m4	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
interp.c	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
local.mk	sim: modules.c: fix generation after recent refactors	2023-01-15 20:55:48 -05:00
machs.c	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
machs.h	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
model_list.def
riscv-sim.h	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
sim-main.c	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
sim-main.h	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00