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https://sourceware.org/git/binutils-gdb.git
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2e4bb98a0e
This patch fixes the routines to collect and supply ptrace registers on ppc64le gdbserver. Originally written for big endian arch, they were causing several issues on little endian. With this fix, the number of unexpected failures in the testsuite dropped from 263 to 72 on ppc64le. gdb/gdbserver/ChangeLog * linux-ppc-low.c (ppc_collect_ptrace_register): Adjust routine to take endianness into account. (ppc_supply_ptrace_register): Likewise.
755 lines
22 KiB
C
755 lines
22 KiB
C
/* GNU/Linux/PowerPC specific low level interface, for the remote server for
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GDB.
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Copyright (C) 1995-2014 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "server.h"
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#include "linux-low.h"
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#include <elf.h>
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#include <asm/ptrace.h>
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/* These are in <asm/cputable.h> in current kernels. */
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#define PPC_FEATURE_HAS_VSX 0x00000080
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
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#define PPC_FEATURE_HAS_SPE 0x00800000
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#define PPC_FEATURE_CELL 0x00010000
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#define PPC_FEATURE_HAS_DFP 0x00000400
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static unsigned long ppc_hwcap;
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/* Defined in auto-generated file powerpc-32l.c. */
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void init_registers_powerpc_32l (void);
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extern const struct target_desc *tdesc_powerpc_32l;
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/* Defined in auto-generated file powerpc-altivec32l.c. */
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void init_registers_powerpc_altivec32l (void);
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extern const struct target_desc *tdesc_powerpc_altivec32l;
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/* Defined in auto-generated file powerpc-cell32l.c. */
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void init_registers_powerpc_cell32l (void);
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extern const struct target_desc *tdesc_powerpc_cell32l;
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/* Defined in auto-generated file powerpc-vsx32l.c. */
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void init_registers_powerpc_vsx32l (void);
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extern const struct target_desc *tdesc_powerpc_vsx32l;
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/* Defined in auto-generated file powerpc-isa205-32l.c. */
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void init_registers_powerpc_isa205_32l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_32l;
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/* Defined in auto-generated file powerpc-isa205-altivec32l.c. */
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void init_registers_powerpc_isa205_altivec32l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_altivec32l;
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/* Defined in auto-generated file powerpc-isa205-vsx32l.c. */
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void init_registers_powerpc_isa205_vsx32l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_vsx32l;
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/* Defined in auto-generated file powerpc-e500l.c. */
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void init_registers_powerpc_e500l (void);
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extern const struct target_desc *tdesc_powerpc_e500l;
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/* Defined in auto-generated file powerpc-64l.c. */
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void init_registers_powerpc_64l (void);
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extern const struct target_desc *tdesc_powerpc_64l;
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/* Defined in auto-generated file powerpc-altivec64l.c. */
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void init_registers_powerpc_altivec64l (void);
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extern const struct target_desc *tdesc_powerpc_altivec64l;
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/* Defined in auto-generated file powerpc-cell64l.c. */
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void init_registers_powerpc_cell64l (void);
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extern const struct target_desc *tdesc_powerpc_cell64l;
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/* Defined in auto-generated file powerpc-vsx64l.c. */
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void init_registers_powerpc_vsx64l (void);
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extern const struct target_desc *tdesc_powerpc_vsx64l;
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/* Defined in auto-generated file powerpc-isa205-64l.c. */
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void init_registers_powerpc_isa205_64l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_64l;
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/* Defined in auto-generated file powerpc-isa205-altivec64l.c. */
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void init_registers_powerpc_isa205_altivec64l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_altivec64l;
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/* Defined in auto-generated file powerpc-isa205-vsx64l.c. */
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void init_registers_powerpc_isa205_vsx64l (void);
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extern const struct target_desc *tdesc_powerpc_isa205_vsx64l;
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#define ppc_num_regs 73
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/* This sometimes isn't defined. */
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#ifndef PT_ORIG_R3
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#define PT_ORIG_R3 34
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#endif
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#ifndef PT_TRAP
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#define PT_TRAP 40
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#endif
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#ifdef __powerpc64__
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/* We use a constant for FPSCR instead of PT_FPSCR, because
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many shipped PPC64 kernels had the wrong value in ptrace.h. */
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static int ppc_regmap[] =
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{PT_R0 * 8, PT_R1 * 8, PT_R2 * 8, PT_R3 * 8,
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PT_R4 * 8, PT_R5 * 8, PT_R6 * 8, PT_R7 * 8,
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PT_R8 * 8, PT_R9 * 8, PT_R10 * 8, PT_R11 * 8,
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PT_R12 * 8, PT_R13 * 8, PT_R14 * 8, PT_R15 * 8,
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PT_R16 * 8, PT_R17 * 8, PT_R18 * 8, PT_R19 * 8,
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PT_R20 * 8, PT_R21 * 8, PT_R22 * 8, PT_R23 * 8,
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PT_R24 * 8, PT_R25 * 8, PT_R26 * 8, PT_R27 * 8,
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PT_R28 * 8, PT_R29 * 8, PT_R30 * 8, PT_R31 * 8,
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PT_FPR0*8, PT_FPR0*8 + 8, PT_FPR0*8+16, PT_FPR0*8+24,
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PT_FPR0*8+32, PT_FPR0*8+40, PT_FPR0*8+48, PT_FPR0*8+56,
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PT_FPR0*8+64, PT_FPR0*8+72, PT_FPR0*8+80, PT_FPR0*8+88,
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PT_FPR0*8+96, PT_FPR0*8+104, PT_FPR0*8+112, PT_FPR0*8+120,
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PT_FPR0*8+128, PT_FPR0*8+136, PT_FPR0*8+144, PT_FPR0*8+152,
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PT_FPR0*8+160, PT_FPR0*8+168, PT_FPR0*8+176, PT_FPR0*8+184,
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PT_FPR0*8+192, PT_FPR0*8+200, PT_FPR0*8+208, PT_FPR0*8+216,
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PT_FPR0*8+224, PT_FPR0*8+232, PT_FPR0*8+240, PT_FPR0*8+248,
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PT_NIP * 8, PT_MSR * 8, PT_CCR * 8, PT_LNK * 8,
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PT_CTR * 8, PT_XER * 8, PT_FPR0*8 + 256,
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PT_ORIG_R3 * 8, PT_TRAP * 8 };
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#else
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/* Currently, don't check/send MQ. */
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static int ppc_regmap[] =
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{PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
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PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
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PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
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PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
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PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
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PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
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PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
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PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
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PT_FPR0*4, PT_FPR0*4 + 8, PT_FPR0*4+16, PT_FPR0*4+24,
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PT_FPR0*4+32, PT_FPR0*4+40, PT_FPR0*4+48, PT_FPR0*4+56,
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PT_FPR0*4+64, PT_FPR0*4+72, PT_FPR0*4+80, PT_FPR0*4+88,
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PT_FPR0*4+96, PT_FPR0*4+104, PT_FPR0*4+112, PT_FPR0*4+120,
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PT_FPR0*4+128, PT_FPR0*4+136, PT_FPR0*4+144, PT_FPR0*4+152,
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PT_FPR0*4+160, PT_FPR0*4+168, PT_FPR0*4+176, PT_FPR0*4+184,
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PT_FPR0*4+192, PT_FPR0*4+200, PT_FPR0*4+208, PT_FPR0*4+216,
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PT_FPR0*4+224, PT_FPR0*4+232, PT_FPR0*4+240, PT_FPR0*4+248,
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PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
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PT_CTR * 4, PT_XER * 4, PT_FPSCR * 4,
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PT_ORIG_R3 * 4, PT_TRAP * 4
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};
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static int ppc_regmap_e500[] =
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{PT_R0 * 4, PT_R1 * 4, PT_R2 * 4, PT_R3 * 4,
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PT_R4 * 4, PT_R5 * 4, PT_R6 * 4, PT_R7 * 4,
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PT_R8 * 4, PT_R9 * 4, PT_R10 * 4, PT_R11 * 4,
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PT_R12 * 4, PT_R13 * 4, PT_R14 * 4, PT_R15 * 4,
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PT_R16 * 4, PT_R17 * 4, PT_R18 * 4, PT_R19 * 4,
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PT_R20 * 4, PT_R21 * 4, PT_R22 * 4, PT_R23 * 4,
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PT_R24 * 4, PT_R25 * 4, PT_R26 * 4, PT_R27 * 4,
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PT_R28 * 4, PT_R29 * 4, PT_R30 * 4, PT_R31 * 4,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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-1, -1, -1, -1,
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PT_NIP * 4, PT_MSR * 4, PT_CCR * 4, PT_LNK * 4,
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PT_CTR * 4, PT_XER * 4, -1,
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PT_ORIG_R3 * 4, PT_TRAP * 4
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};
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#endif
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static int
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ppc_cannot_store_register (int regno)
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{
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const struct target_desc *tdesc = current_process ()->tdesc;
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#ifndef __powerpc64__
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/* Some kernels do not allow us to store fpscr. */
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if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE)
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&& regno == find_regno (tdesc, "fpscr"))
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return 2;
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#endif
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/* Some kernels do not allow us to store orig_r3 or trap. */
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if (regno == find_regno (tdesc, "orig_r3")
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|| regno == find_regno (tdesc, "trap"))
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return 2;
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return 0;
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}
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static int
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ppc_cannot_fetch_register (int regno)
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{
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return 0;
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}
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static void
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ppc_collect_ptrace_register (struct regcache *regcache, int regno, char *buf)
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{
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memset (buf, 0, sizeof (long));
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if (__BYTE_ORDER == __LITTLE_ENDIAN)
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{
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/* Little-endian values always sit at the left end of the buffer. */
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collect_register (regcache, regno, buf);
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}
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else if (__BYTE_ORDER == __BIG_ENDIAN)
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{
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/* Big-endian values sit at the right end of the buffer. In case of
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registers whose sizes are smaller than sizeof (long), we must use a
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padding to access them correctly. */
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int size = register_size (regcache->tdesc, regno);
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if (size < sizeof (long))
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collect_register (regcache, regno, buf + sizeof (long) - size);
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else
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collect_register (regcache, regno, buf);
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}
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else
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perror_with_name ("Unexpected byte order");
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}
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static void
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ppc_supply_ptrace_register (struct regcache *regcache,
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int regno, const char *buf)
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{
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if (__BYTE_ORDER == __LITTLE_ENDIAN)
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{
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/* Little-endian values always sit at the left end of the buffer. */
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supply_register (regcache, regno, buf);
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}
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else if (__BYTE_ORDER == __BIG_ENDIAN)
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{
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/* Big-endian values sit at the right end of the buffer. In case of
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registers whose sizes are smaller than sizeof (long), we must use a
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padding to access them correctly. */
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int size = register_size (regcache->tdesc, regno);
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if (size < sizeof (long))
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supply_register (regcache, regno, buf + sizeof (long) - size);
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else
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supply_register (regcache, regno, buf);
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}
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else
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perror_with_name ("Unexpected byte order");
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}
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#define INSTR_SC 0x44000002
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#define NR_spu_run 0x0116
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/* If the PPU thread is currently stopped on a spu_run system call,
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return to FD and ADDR the file handle and NPC parameter address
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used with the system call. Return non-zero if successful. */
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static int
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parse_spufs_run (struct regcache *regcache, int *fd, CORE_ADDR *addr)
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{
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CORE_ADDR curr_pc;
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int curr_insn;
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int curr_r0;
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if (register_size (regcache->tdesc, 0) == 4)
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{
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unsigned int pc, r0, r3, r4;
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collect_register_by_name (regcache, "pc", &pc);
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collect_register_by_name (regcache, "r0", &r0);
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collect_register_by_name (regcache, "orig_r3", &r3);
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collect_register_by_name (regcache, "r4", &r4);
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curr_pc = (CORE_ADDR) pc;
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curr_r0 = (int) r0;
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*fd = (int) r3;
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*addr = (CORE_ADDR) r4;
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}
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else
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{
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unsigned long pc, r0, r3, r4;
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collect_register_by_name (regcache, "pc", &pc);
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collect_register_by_name (regcache, "r0", &r0);
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collect_register_by_name (regcache, "orig_r3", &r3);
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collect_register_by_name (regcache, "r4", &r4);
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curr_pc = (CORE_ADDR) pc;
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curr_r0 = (int) r0;
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*fd = (int) r3;
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*addr = (CORE_ADDR) r4;
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}
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/* Fetch instruction preceding current NIP. */
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if ((*the_target->read_memory) (curr_pc - 4,
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(unsigned char *) &curr_insn, 4) != 0)
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return 0;
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/* It should be a "sc" instruction. */
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if (curr_insn != INSTR_SC)
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return 0;
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/* System call number should be NR_spu_run. */
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if (curr_r0 != NR_spu_run)
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return 0;
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return 1;
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}
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static CORE_ADDR
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ppc_get_pc (struct regcache *regcache)
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{
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CORE_ADDR addr;
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int fd;
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if (parse_spufs_run (regcache, &fd, &addr))
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{
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unsigned int pc;
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(*the_target->read_memory) (addr, (unsigned char *) &pc, 4);
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return ((CORE_ADDR)1 << 63)
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| ((CORE_ADDR)fd << 32) | (CORE_ADDR) (pc - 4);
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}
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else if (register_size (regcache->tdesc, 0) == 4)
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{
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unsigned int pc;
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collect_register_by_name (regcache, "pc", &pc);
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return (CORE_ADDR) pc;
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}
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else
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{
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unsigned long pc;
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collect_register_by_name (regcache, "pc", &pc);
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return (CORE_ADDR) pc;
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}
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}
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static void
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ppc_set_pc (struct regcache *regcache, CORE_ADDR pc)
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{
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CORE_ADDR addr;
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int fd;
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if (parse_spufs_run (regcache, &fd, &addr))
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{
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unsigned int newpc = pc;
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(*the_target->write_memory) (addr, (unsigned char *) &newpc, 4);
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}
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else if (register_size (regcache->tdesc, 0) == 4)
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{
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unsigned int newpc = pc;
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supply_register_by_name (regcache, "pc", &newpc);
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}
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else
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{
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unsigned long newpc = pc;
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supply_register_by_name (regcache, "pc", &newpc);
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}
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}
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static int
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ppc_get_hwcap (unsigned long *valp)
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{
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const struct target_desc *tdesc = current_process ()->tdesc;
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int wordsize = register_size (tdesc, 0);
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unsigned char *data = alloca (2 * wordsize);
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int offset = 0;
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while ((*the_target->read_auxv) (offset, data, 2 * wordsize) == 2 * wordsize)
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{
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if (wordsize == 4)
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{
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unsigned int *data_p = (unsigned int *)data;
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if (data_p[0] == AT_HWCAP)
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{
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*valp = data_p[1];
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return 1;
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}
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}
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else
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{
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unsigned long *data_p = (unsigned long *)data;
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if (data_p[0] == AT_HWCAP)
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{
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*valp = data_p[1];
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return 1;
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}
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}
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offset += 2 * wordsize;
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}
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*valp = 0;
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return 0;
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}
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/* Forward declaration. */
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static struct usrregs_info ppc_usrregs_info;
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#ifndef __powerpc64__
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static int ppc_regmap_adjusted;
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#endif
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static void
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ppc_arch_setup (void)
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{
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const struct target_desc *tdesc;
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#ifdef __powerpc64__
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long msr;
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struct regcache *regcache;
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/* On a 64-bit host, assume 64-bit inferior process with no
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AltiVec registers. Reset ppc_hwcap to ensure that the
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collect_register call below does not fail. */
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tdesc = tdesc_powerpc_64l;
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current_process ()->tdesc = tdesc;
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ppc_hwcap = 0;
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/* Only if the high bit of the MSR is set, we actually have
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a 64-bit inferior. */
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regcache = new_register_cache (tdesc);
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fetch_inferior_registers (regcache, find_regno (tdesc, "msr"));
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collect_register_by_name (regcache, "msr", &msr);
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free_register_cache (regcache);
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|
if (msr < 0)
|
|
{
|
|
ppc_get_hwcap (&ppc_hwcap);
|
|
if (ppc_hwcap & PPC_FEATURE_CELL)
|
|
tdesc = tdesc_powerpc_cell64l;
|
|
else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
|
|
{
|
|
/* Power ISA 2.05 (implemented by Power 6 and newer processors)
|
|
increases the FPSCR from 32 bits to 64 bits. Even though Power 7
|
|
supports this ISA version, it doesn't have PPC_FEATURE_ARCH_2_05
|
|
set, only PPC_FEATURE_ARCH_2_06. Since for now the only bits
|
|
used in the higher half of the register are for Decimal Floating
|
|
Point, we check if that feature is available to decide the size
|
|
of the FPSCR. */
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
|
|
tdesc = tdesc_powerpc_isa205_vsx64l;
|
|
else
|
|
tdesc = tdesc_powerpc_vsx64l;
|
|
}
|
|
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
|
|
{
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
|
|
tdesc = tdesc_powerpc_isa205_altivec64l;
|
|
else
|
|
tdesc = tdesc_powerpc_altivec64l;
|
|
}
|
|
|
|
current_process ()->tdesc = tdesc;
|
|
return;
|
|
}
|
|
#endif
|
|
|
|
/* OK, we have a 32-bit inferior. */
|
|
tdesc = tdesc_powerpc_32l;
|
|
current_process ()->tdesc = tdesc;
|
|
|
|
ppc_get_hwcap (&ppc_hwcap);
|
|
if (ppc_hwcap & PPC_FEATURE_CELL)
|
|
tdesc = tdesc_powerpc_cell32l;
|
|
else if (ppc_hwcap & PPC_FEATURE_HAS_VSX)
|
|
{
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
|
|
tdesc = tdesc_powerpc_isa205_vsx32l;
|
|
else
|
|
tdesc = tdesc_powerpc_vsx32l;
|
|
}
|
|
else if (ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC)
|
|
{
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_DFP)
|
|
tdesc = tdesc_powerpc_isa205_altivec32l;
|
|
else
|
|
tdesc = tdesc_powerpc_altivec32l;
|
|
}
|
|
|
|
/* On 32-bit machines, check for SPE registers.
|
|
Set the low target's regmap field as appropriately. */
|
|
#ifndef __powerpc64__
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
|
|
tdesc = tdesc_powerpc_e500l;
|
|
|
|
if (!ppc_regmap_adjusted)
|
|
{
|
|
if (ppc_hwcap & PPC_FEATURE_HAS_SPE)
|
|
ppc_usrregs_info.regmap = ppc_regmap_e500;
|
|
|
|
/* If the FPSCR is 64-bit wide, we need to fetch the whole
|
|
64-bit slot and not just its second word. The PT_FPSCR
|
|
supplied in a 32-bit GDB compilation doesn't reflect
|
|
this. */
|
|
if (register_size (tdesc, 70) == 8)
|
|
ppc_regmap[70] = (48 + 2*32) * sizeof (long);
|
|
|
|
ppc_regmap_adjusted = 1;
|
|
}
|
|
#endif
|
|
current_process ()->tdesc = tdesc;
|
|
}
|
|
|
|
/* Correct in either endianness.
|
|
This instruction is "twge r2, r2", which GDB uses as a software
|
|
breakpoint. */
|
|
static const unsigned int ppc_breakpoint = 0x7d821008;
|
|
#define ppc_breakpoint_len 4
|
|
|
|
static int
|
|
ppc_breakpoint_at (CORE_ADDR where)
|
|
{
|
|
unsigned int insn;
|
|
|
|
if (where & ((CORE_ADDR)1 << 63))
|
|
{
|
|
char mem_annex[32];
|
|
sprintf (mem_annex, "%d/mem", (int)((where >> 32) & 0x7fffffff));
|
|
(*the_target->qxfer_spu) (mem_annex, (unsigned char *) &insn,
|
|
NULL, where & 0xffffffff, 4);
|
|
if (insn == 0x3fff)
|
|
return 1;
|
|
}
|
|
else
|
|
{
|
|
(*the_target->read_memory) (where, (unsigned char *) &insn, 4);
|
|
if (insn == ppc_breakpoint)
|
|
return 1;
|
|
/* If necessary, recognize more trap instructions here. GDB only uses
|
|
the one. */
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Provide only a fill function for the general register set. ps_lgetregs
|
|
will use this for NPTL support. */
|
|
|
|
static void ppc_fill_gregset (struct regcache *regcache, void *buf)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < 32; i++)
|
|
ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
|
|
|
|
for (i = 64; i < 70; i++)
|
|
ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
|
|
|
|
for (i = 71; i < 73; i++)
|
|
ppc_collect_ptrace_register (regcache, i, (char *) buf + ppc_regmap[i]);
|
|
}
|
|
|
|
#ifndef PTRACE_GETVSXREGS
|
|
#define PTRACE_GETVSXREGS 27
|
|
#define PTRACE_SETVSXREGS 28
|
|
#endif
|
|
|
|
#define SIZEOF_VSXREGS 32*8
|
|
|
|
static void
|
|
ppc_fill_vsxregset (struct regcache *regcache, void *buf)
|
|
{
|
|
int i, base;
|
|
char *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
|
|
return;
|
|
|
|
base = find_regno (regcache->tdesc, "vs0h");
|
|
for (i = 0; i < 32; i++)
|
|
collect_register (regcache, base + i, ®set[i * 8]);
|
|
}
|
|
|
|
static void
|
|
ppc_store_vsxregset (struct regcache *regcache, const void *buf)
|
|
{
|
|
int i, base;
|
|
const char *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_VSX))
|
|
return;
|
|
|
|
base = find_regno (regcache->tdesc, "vs0h");
|
|
for (i = 0; i < 32; i++)
|
|
supply_register (regcache, base + i, ®set[i * 8]);
|
|
}
|
|
|
|
#ifndef PTRACE_GETVRREGS
|
|
#define PTRACE_GETVRREGS 18
|
|
#define PTRACE_SETVRREGS 19
|
|
#endif
|
|
|
|
#define SIZEOF_VRREGS 33*16+4
|
|
|
|
static void
|
|
ppc_fill_vrregset (struct regcache *regcache, void *buf)
|
|
{
|
|
int i, base;
|
|
char *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
|
|
return;
|
|
|
|
base = find_regno (regcache->tdesc, "vr0");
|
|
for (i = 0; i < 32; i++)
|
|
collect_register (regcache, base + i, ®set[i * 16]);
|
|
|
|
collect_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]);
|
|
collect_register_by_name (regcache, "vrsave", ®set[33 * 16]);
|
|
}
|
|
|
|
static void
|
|
ppc_store_vrregset (struct regcache *regcache, const void *buf)
|
|
{
|
|
int i, base;
|
|
const char *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_ALTIVEC))
|
|
return;
|
|
|
|
base = find_regno (regcache->tdesc, "vr0");
|
|
for (i = 0; i < 32; i++)
|
|
supply_register (regcache, base + i, ®set[i * 16]);
|
|
|
|
supply_register_by_name (regcache, "vscr", ®set[32 * 16 + 12]);
|
|
supply_register_by_name (regcache, "vrsave", ®set[33 * 16]);
|
|
}
|
|
|
|
#ifndef PTRACE_GETEVRREGS
|
|
#define PTRACE_GETEVRREGS 20
|
|
#define PTRACE_SETEVRREGS 21
|
|
#endif
|
|
|
|
struct gdb_evrregset_t
|
|
{
|
|
unsigned long evr[32];
|
|
unsigned long long acc;
|
|
unsigned long spefscr;
|
|
};
|
|
|
|
static void
|
|
ppc_fill_evrregset (struct regcache *regcache, void *buf)
|
|
{
|
|
int i, ev0;
|
|
struct gdb_evrregset_t *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
|
|
return;
|
|
|
|
ev0 = find_regno (regcache->tdesc, "ev0h");
|
|
for (i = 0; i < 32; i++)
|
|
collect_register (regcache, ev0 + i, ®set->evr[i]);
|
|
|
|
collect_register_by_name (regcache, "acc", ®set->acc);
|
|
collect_register_by_name (regcache, "spefscr", ®set->spefscr);
|
|
}
|
|
|
|
static void
|
|
ppc_store_evrregset (struct regcache *regcache, const void *buf)
|
|
{
|
|
int i, ev0;
|
|
const struct gdb_evrregset_t *regset = buf;
|
|
|
|
if (!(ppc_hwcap & PPC_FEATURE_HAS_SPE))
|
|
return;
|
|
|
|
ev0 = find_regno (regcache->tdesc, "ev0h");
|
|
for (i = 0; i < 32; i++)
|
|
supply_register (regcache, ev0 + i, ®set->evr[i]);
|
|
|
|
supply_register_by_name (regcache, "acc", ®set->acc);
|
|
supply_register_by_name (regcache, "spefscr", ®set->spefscr);
|
|
}
|
|
|
|
static struct regset_info ppc_regsets[] = {
|
|
/* List the extra register sets before GENERAL_REGS. That way we will
|
|
fetch them every time, but still fall back to PTRACE_PEEKUSER for the
|
|
general registers. Some kernels support these, but not the newer
|
|
PPC_PTRACE_GETREGS. */
|
|
{ PTRACE_GETVSXREGS, PTRACE_SETVSXREGS, 0, SIZEOF_VSXREGS, EXTENDED_REGS,
|
|
ppc_fill_vsxregset, ppc_store_vsxregset },
|
|
{ PTRACE_GETVRREGS, PTRACE_SETVRREGS, 0, SIZEOF_VRREGS, EXTENDED_REGS,
|
|
ppc_fill_vrregset, ppc_store_vrregset },
|
|
{ PTRACE_GETEVRREGS, PTRACE_SETEVRREGS, 0, 32 * 4 + 8 + 4, EXTENDED_REGS,
|
|
ppc_fill_evrregset, ppc_store_evrregset },
|
|
{ 0, 0, 0, 0, GENERAL_REGS, ppc_fill_gregset, NULL },
|
|
{ 0, 0, 0, -1, -1, NULL, NULL }
|
|
};
|
|
|
|
static struct usrregs_info ppc_usrregs_info =
|
|
{
|
|
ppc_num_regs,
|
|
ppc_regmap,
|
|
};
|
|
|
|
static struct regsets_info ppc_regsets_info =
|
|
{
|
|
ppc_regsets, /* regsets */
|
|
0, /* num_regsets */
|
|
NULL, /* disabled_regsets */
|
|
};
|
|
|
|
static struct regs_info regs_info =
|
|
{
|
|
NULL, /* regset_bitmap */
|
|
&ppc_usrregs_info,
|
|
&ppc_regsets_info
|
|
};
|
|
|
|
static const struct regs_info *
|
|
ppc_regs_info (void)
|
|
{
|
|
return ®s_info;
|
|
}
|
|
|
|
struct linux_target_ops the_low_target = {
|
|
ppc_arch_setup,
|
|
ppc_regs_info,
|
|
ppc_cannot_fetch_register,
|
|
ppc_cannot_store_register,
|
|
NULL, /* fetch_register */
|
|
ppc_get_pc,
|
|
ppc_set_pc,
|
|
(const unsigned char *) &ppc_breakpoint,
|
|
ppc_breakpoint_len,
|
|
NULL,
|
|
0,
|
|
ppc_breakpoint_at,
|
|
NULL, /* supports_z_point_type */
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
NULL,
|
|
ppc_collect_ptrace_register,
|
|
ppc_supply_ptrace_register,
|
|
};
|
|
|
|
void
|
|
initialize_low_arch (void)
|
|
{
|
|
/* Initialize the Linux target descriptions. */
|
|
|
|
init_registers_powerpc_32l ();
|
|
init_registers_powerpc_altivec32l ();
|
|
init_registers_powerpc_cell32l ();
|
|
init_registers_powerpc_vsx32l ();
|
|
init_registers_powerpc_isa205_32l ();
|
|
init_registers_powerpc_isa205_altivec32l ();
|
|
init_registers_powerpc_isa205_vsx32l ();
|
|
init_registers_powerpc_e500l ();
|
|
init_registers_powerpc_64l ();
|
|
init_registers_powerpc_altivec64l ();
|
|
init_registers_powerpc_cell64l ();
|
|
init_registers_powerpc_vsx64l ();
|
|
init_registers_powerpc_isa205_64l ();
|
|
init_registers_powerpc_isa205_altivec64l ();
|
|
init_registers_powerpc_isa205_vsx64l ();
|
|
|
|
initialize_regsets_info (&ppc_regsets_info);
|
|
}
|