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1204 lines
30 KiB
C
1204 lines
30 KiB
C
/* Instruction printing code for the ARM
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Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
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Free Software Foundation, Inc.
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Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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Modification by James G. Smith (jsmith@cygnus.co.uk)
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This file is part of libopcodes.
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#define DEFINE_TABLE
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#include "arm-opc.h"
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#include "coff/internal.h"
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#include "libcoff.h"
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#include "opintl.h"
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/* FIXME: This shouldn't be done here */
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#include "elf-bfd.h"
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#include "elf/internal.h"
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#include "elf/arm.h"
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#ifndef streq
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#endif
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#ifndef strneq
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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#ifndef NUM_ELEM
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#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
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#endif
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static char * arm_conditional[] =
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{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "", "nv"};
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typedef struct
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{
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const char * name;
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const char * description;
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const char * reg_names[16];
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}
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arm_regname;
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static arm_regname regnames[] =
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{
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{ "raw" , "Select raw register names",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
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{ "gcc", "Select register names used by GCC",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
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{ "std", "Select register names used in ARM's ISA documentation",
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
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{ "apcs", "Select register names used in the APCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
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{ "atpcs", "Select register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
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{ "special-atpcs", "Select special register names used in the ATPCS",
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{ "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
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};
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/* Default to GCC register name set. */
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static unsigned int regname_selected = 1;
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#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
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#define arm_regnames regnames[regname_selected].reg_names
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static boolean force_thumb = false;
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static char * arm_fp_const[] =
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{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
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static char * arm_shift[] =
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{"lsl", "lsr", "asr", "ror"};
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/* Forward declarations. */
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static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *));
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static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long));
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static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long));
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static void parse_disassembler_options PARAMS ((char *));
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static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean));
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int get_arm_regname_num_options (void);
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int set_arm_regname_option (int option);
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int get_arm_regnames (int option, const char **setname,
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const char **setdescription,
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const char ***register_names);
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/* Functions. */
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int
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get_arm_regname_num_options (void)
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{
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return NUM_ARM_REGNAMES;
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}
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int
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set_arm_regname_option (int option)
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{
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int old = regname_selected;
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regname_selected = option;
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return old;
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}
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int
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get_arm_regnames (int option, const char **setname,
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const char **setdescription,
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const char ***register_names)
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{
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*setname = regnames[option].name;
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*setdescription = regnames[option].description;
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*register_names = regnames[option].reg_names;
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return 16;
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}
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static void
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arm_decode_shift (given, func, stream)
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long given;
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fprintf_ftype func;
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void * stream;
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{
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func (stream, "%s", arm_regnames[given & 0xf]);
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if ((given & 0xff0) != 0)
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{
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if ((given & 0x10) == 0)
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{
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int amount = (given & 0xf80) >> 7;
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int shift = (given & 0x60) >> 5;
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if (amount == 0)
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{
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if (shift == 3)
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{
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func (stream, ", rrx");
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return;
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}
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amount = 32;
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}
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func (stream, ", %s #%d", arm_shift[shift], amount);
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}
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else
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func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
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arm_regnames[(given & 0xf00) >> 8]);
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}
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction (always 4 on ARM). */
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static int
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print_insn_arm (pc, info, given)
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bfd_vma pc;
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struct disassemble_info * info;
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long given;
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{
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struct arm_opcode * insn;
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void * stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = arm_opcodes; insn->assembler; insn++)
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{
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if ((given & insn->mask) == insn->value)
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{
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char * c;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case '%':
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func (stream, "%%");
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break;
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case 'a':
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if (((given & 0x000f0000) == 0x000f0000)
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&& ((given & 0x02000000) == 0))
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{
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int offset = given & 0xfff;
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func (stream, "[pc");
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if (given & 0x01000000)
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{
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if ((given & 0x00800000) == 0)
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offset = - offset;
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/* pre-indexed */
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func (stream, ", #%d]", offset);
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offset += pc + 8;
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/* Cope with the possibility of write-back
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being used. Probably a very dangerous thing
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for the programmer to do, but who are we to
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argue ? */
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if (given & 0x00200000)
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func (stream, "!");
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}
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else
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{
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/* Post indexed. */
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func (stream, "], #%d", offset);
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offset = pc + 8; /* ie ignore the offset. */
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}
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func (stream, "\t; ");
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info->print_address_func (offset, info);
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}
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else
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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if ((given & 0x02000000) == 0)
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{
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int offset = given & 0xfff;
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if (offset)
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func (stream, ", %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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}
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else
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{
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func (stream, ", %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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}
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else
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{
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if ((given & 0x02000000) == 0)
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{
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int offset = given & 0xfff;
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if (offset)
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func (stream, "], %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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else
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func (stream, "]");
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}
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else
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{
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func (stream, "], %s",
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(((given & 0x00800000) == 0)
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? "-" : ""));
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arm_decode_shift (given, func, stream);
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}
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}
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}
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break;
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case 's':
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if ((given & 0x004f0000) == 0x004f0000)
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{
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/* PC relative with immediate offset. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if ((given & 0x00800000) == 0)
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offset = -offset;
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func (stream, "[pc, #%d]\t; ", offset);
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(*info->print_address_func)
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(offset + pc + 8, info);
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}
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else
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{
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func (stream, "[%s",
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arm_regnames[(given >> 16) & 0xf]);
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if ((given & 0x01000000) != 0)
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{
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/* Pre-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* Immediate. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, ", %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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}
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else
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{
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/* Register. */
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func (stream, ", %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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arm_regnames[given & 0xf]);
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}
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func (stream, "]%s",
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((given & 0x00200000) != 0) ? "!" : "");
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}
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else
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{
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/* Post-indexed. */
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if ((given & 0x00400000) == 0x00400000)
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{
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/* Immediate. */
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int offset = ((given & 0xf00) >> 4) | (given & 0xf);
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if (offset)
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func (stream, "], %s#%d",
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(((given & 0x00800000) == 0)
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? "-" : ""), offset);
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else
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func (stream, "]");
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}
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else
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{
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/* Register. */
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func (stream, "], %s%s",
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(((given & 0x00800000) == 0)
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? "-" : ""),
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arm_regnames[given & 0xf]);
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}
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}
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}
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break;
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case 'b':
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(*info->print_address_func)
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(BDISP (given) * 4 + pc + 8, info);
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break;
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case 'c':
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func (stream, "%s",
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arm_conditional [(given >> 28) & 0xf]);
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break;
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case 'm':
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{
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int started = 0;
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int reg;
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func (stream, "{");
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for (reg = 0; reg < 16; reg++)
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if ((given & (1 << reg)) != 0)
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{
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if (started)
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func (stream, ", ");
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started = 1;
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func (stream, "%s", arm_regnames[reg]);
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}
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func (stream, "}");
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||
}
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break;
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||
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||
case 'o':
|
||
if ((given & 0x02000000) != 0)
|
||
{
|
||
int rotate = (given & 0xf00) >> 7;
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||
int immed = (given & 0xff);
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immed = (((immed << (32 - rotate))
|
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| (immed >> rotate)) & 0xffffffff);
|
||
func (stream, "#%d\t; 0x%x", immed, immed);
|
||
}
|
||
else
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arm_decode_shift (given, func, stream);
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break;
|
||
|
||
case 'p':
|
||
if ((given & 0x0000f000) == 0x0000f000)
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||
func (stream, "p");
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||
break;
|
||
|
||
case 't':
|
||
if ((given & 0x01200000) == 0x00200000)
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||
func (stream, "t");
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||
break;
|
||
|
||
case 'A':
|
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func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
|
||
if ((given & 0x01000000) != 0)
|
||
{
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||
int offset = given & 0xff;
|
||
if (offset)
|
||
func (stream, ", %s#%d]%s",
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((given & 0x00800000) == 0 ? "-" : ""),
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||
offset * 4,
|
||
((given & 0x00200000) != 0 ? "!" : ""));
|
||
else
|
||
func (stream, "]");
|
||
}
|
||
else
|
||
{
|
||
int offset = given & 0xff;
|
||
if (offset)
|
||
func (stream, "], %s#%d",
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||
((given & 0x00800000) == 0 ? "-" : ""),
|
||
offset * 4);
|
||
else
|
||
func (stream, "]");
|
||
}
|
||
break;
|
||
|
||
case 'B':
|
||
/* Print ARM V5 BLX(1) address: pc+25 bits. */
|
||
{
|
||
bfd_vma address;
|
||
bfd_vma offset = 0;
|
||
|
||
if (given & 0x00800000)
|
||
/* Is signed, hi bits should be ones. */
|
||
offset = (-1) ^ 0x00ffffff;
|
||
|
||
/* Offset is (SignExtend(offset field)<<2). */
|
||
offset += given & 0x00ffffff;
|
||
offset <<= 2;
|
||
address = offset + pc + 8;
|
||
|
||
if (given & 0x01000000)
|
||
/* H bit allows addressing to 2-byte boundaries. */
|
||
address += 2;
|
||
|
||
info->print_address_func (address, info);
|
||
}
|
||
break;
|
||
|
||
case 'I':
|
||
/* Print a Cirrus/DSP shift immediate. */
|
||
/* Immediates are 7bit signed ints with bits 0..3 in
|
||
bits 0..3 of opcode and bits 4..6 in bits 5..7
|
||
of opcode. */
|
||
{
|
||
int imm;
|
||
|
||
imm = (given & 0xf) | ((given & 0xe0) >> 1);
|
||
|
||
/* Is ``imm'' a negative number? */
|
||
if (imm & 0x40)
|
||
imm |= (-1 << 7);
|
||
|
||
func (stream, "%d", imm);
|
||
}
|
||
|
||
break;
|
||
|
||
case 'C':
|
||
func (stream, "_");
|
||
if (given & 0x80000)
|
||
func (stream, "f");
|
||
if (given & 0x40000)
|
||
func (stream, "s");
|
||
if (given & 0x20000)
|
||
func (stream, "x");
|
||
if (given & 0x10000)
|
||
func (stream, "c");
|
||
break;
|
||
|
||
case 'F':
|
||
switch (given & 0x00408000)
|
||
{
|
||
case 0:
|
||
func (stream, "4");
|
||
break;
|
||
case 0x8000:
|
||
func (stream, "1");
|
||
break;
|
||
case 0x00400000:
|
||
func (stream, "2");
|
||
break;
|
||
default:
|
||
func (stream, "3");
|
||
}
|
||
break;
|
||
|
||
case 'P':
|
||
switch (given & 0x00080080)
|
||
{
|
||
case 0:
|
||
func (stream, "s");
|
||
break;
|
||
case 0x80:
|
||
func (stream, "d");
|
||
break;
|
||
case 0x00080000:
|
||
func (stream, "e");
|
||
break;
|
||
default:
|
||
func (stream, _("<illegal precision>"));
|
||
break;
|
||
}
|
||
break;
|
||
case 'Q':
|
||
switch (given & 0x00408000)
|
||
{
|
||
case 0:
|
||
func (stream, "s");
|
||
break;
|
||
case 0x8000:
|
||
func (stream, "d");
|
||
break;
|
||
case 0x00400000:
|
||
func (stream, "e");
|
||
break;
|
||
default:
|
||
func (stream, "p");
|
||
break;
|
||
}
|
||
break;
|
||
case 'R':
|
||
switch (given & 0x60)
|
||
{
|
||
case 0:
|
||
break;
|
||
case 0x20:
|
||
func (stream, "p");
|
||
break;
|
||
case 0x40:
|
||
func (stream, "m");
|
||
break;
|
||
default:
|
||
func (stream, "z");
|
||
break;
|
||
}
|
||
break;
|
||
|
||
case '0': case '1': case '2': case '3': case '4':
|
||
case '5': case '6': case '7': case '8': case '9':
|
||
{
|
||
int bitstart = *c++ - '0';
|
||
int bitend = 0;
|
||
while (*c >= '0' && *c <= '9')
|
||
bitstart = (bitstart * 10) + *c++ - '0';
|
||
|
||
switch (*c)
|
||
{
|
||
case '-':
|
||
c++;
|
||
|
||
while (*c >= '0' && *c <= '9')
|
||
bitend = (bitend * 10) + *c++ - '0';
|
||
|
||
if (!bitend)
|
||
abort ();
|
||
|
||
switch (*c)
|
||
{
|
||
case 'r':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
case 'd':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%d", reg);
|
||
}
|
||
break;
|
||
case 'x':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "0x%08x", reg);
|
||
|
||
/* Some SWI instructions have special
|
||
meanings. */
|
||
if ((given & 0x0fffffff) == 0x0FF00000)
|
||
func (stream, "\t; IMB");
|
||
else if ((given & 0x0fffffff) == 0x0FF00001)
|
||
func (stream, "\t; IMBRange");
|
||
}
|
||
break;
|
||
case 'X':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
func (stream, "%01x", reg & 0xf);
|
||
}
|
||
break;
|
||
case 'f':
|
||
{
|
||
long reg;
|
||
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
|
||
if (reg > 7)
|
||
func (stream, "#%s",
|
||
arm_fp_const[reg & 7]);
|
||
else
|
||
func (stream, "f%d", reg);
|
||
}
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
break;
|
||
|
||
case 'y':
|
||
case 'z':
|
||
{
|
||
int single = *c == 'y';
|
||
int regno;
|
||
|
||
switch (bitstart)
|
||
{
|
||
case 4: /* Sm pair */
|
||
func (stream, "{");
|
||
/* Fall through. */
|
||
case 0: /* Sm, Dm */
|
||
regno = given & 0x0000000f;
|
||
if (single)
|
||
{
|
||
regno <<= 1;
|
||
regno += (given >> 5) & 1;
|
||
}
|
||
break;
|
||
|
||
case 1: /* Sd, Dd */
|
||
regno = (given >> 12) & 0x0000000f;
|
||
if (single)
|
||
{
|
||
regno <<= 1;
|
||
regno += (given >> 22) & 1;
|
||
}
|
||
break;
|
||
|
||
case 2: /* Sn, Dn */
|
||
regno = (given >> 16) & 0x0000000f;
|
||
if (single)
|
||
{
|
||
regno <<= 1;
|
||
regno += (given >> 7) & 1;
|
||
}
|
||
break;
|
||
|
||
case 3: /* List */
|
||
func (stream, "{");
|
||
regno = (given >> 12) & 0x0000000f;
|
||
if (single)
|
||
{
|
||
regno <<= 1;
|
||
regno += (given >> 22) & 1;
|
||
}
|
||
break;
|
||
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
|
||
func (stream, "%c%d", single ? 's' : 'd', regno);
|
||
|
||
if (bitstart == 3)
|
||
{
|
||
int count = given & 0xff;
|
||
|
||
if (single == 0)
|
||
count >>= 1;
|
||
|
||
if (--count)
|
||
{
|
||
func (stream, "-%c%d",
|
||
single ? 's' : 'd',
|
||
regno + count);
|
||
}
|
||
|
||
func (stream, "}");
|
||
}
|
||
else if (bitstart == 4)
|
||
func (stream, ", %c%d}", single ? 's' : 'd',
|
||
regno + 1);
|
||
|
||
break;
|
||
}
|
||
|
||
case '`':
|
||
c++;
|
||
if ((given & (1 << bitstart)) == 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
case '\'':
|
||
c++;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
case '?':
|
||
++c;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c++);
|
||
else
|
||
func (stream, "%c", *++c);
|
||
break;
|
||
default:
|
||
abort ();
|
||
}
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
}
|
||
else
|
||
func (stream, "%c", *c);
|
||
}
|
||
return 4;
|
||
}
|
||
}
|
||
abort ();
|
||
}
|
||
|
||
/* Print one instruction from PC on INFO->STREAM.
|
||
Return the size of the instruction. */
|
||
static int
|
||
print_insn_thumb (pc, info, given)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
long given;
|
||
{
|
||
struct thumb_opcode * insn;
|
||
void * stream = info->stream;
|
||
fprintf_ftype func = info->fprintf_func;
|
||
|
||
for (insn = thumb_opcodes; insn->assembler; insn++)
|
||
{
|
||
if ((given & insn->mask) == insn->value)
|
||
{
|
||
char * c = insn->assembler;
|
||
|
||
/* Special processing for Thumb 2 instruction BL sequence: */
|
||
if (!*c) /* Check for empty (not NULL) assembler string. */
|
||
{
|
||
long offset;
|
||
|
||
info->bytes_per_chunk = 4;
|
||
info->bytes_per_line = 4;
|
||
|
||
offset = BDISP23 (given);
|
||
|
||
if ((given & 0x10000000) == 0)
|
||
{
|
||
func (stream, "blx\t");
|
||
|
||
/* The spec says that bit 1 of the branch's destination
|
||
address comes from bit 1 of the instruction's
|
||
address and not from the offset in the instruction. */
|
||
if (offset & 0x1)
|
||
{
|
||
/* func (stream, "*malformed!* "); */
|
||
offset &= ~ 0x1;
|
||
}
|
||
|
||
offset |= ((pc & 0x2) >> 1);
|
||
}
|
||
else
|
||
func (stream, "bl\t");
|
||
|
||
info->print_address_func (offset * 2 + pc + 4, info);
|
||
return 4;
|
||
}
|
||
else
|
||
{
|
||
info->bytes_per_chunk = 2;
|
||
info->bytes_per_line = 4;
|
||
|
||
given &= 0xffff;
|
||
|
||
for (; *c; c++)
|
||
{
|
||
if (*c == '%')
|
||
{
|
||
int domaskpc = 0;
|
||
int domasklr = 0;
|
||
|
||
switch (*++c)
|
||
{
|
||
case '%':
|
||
func (stream, "%%");
|
||
break;
|
||
|
||
case 'S':
|
||
{
|
||
long reg;
|
||
|
||
reg = (given >> 3) & 0x7;
|
||
if (given & (1 << 6))
|
||
reg += 8;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
|
||
case 'D':
|
||
{
|
||
long reg;
|
||
|
||
reg = given & 0x7;
|
||
if (given & (1 << 7))
|
||
reg += 8;
|
||
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
break;
|
||
|
||
case 'T':
|
||
func (stream, "%s",
|
||
arm_conditional [(given >> 8) & 0xf]);
|
||
break;
|
||
|
||
case 'N':
|
||
if (given & (1 << 8))
|
||
domasklr = 1;
|
||
/* Fall through. */
|
||
case 'O':
|
||
if (*c == 'O' && (given & (1 << 8)))
|
||
domaskpc = 1;
|
||
/* Fall through. */
|
||
case 'M':
|
||
{
|
||
int started = 0;
|
||
int reg;
|
||
|
||
func (stream, "{");
|
||
|
||
/* It would be nice if we could spot
|
||
ranges, and generate the rS-rE format: */
|
||
for (reg = 0; (reg < 8); reg++)
|
||
if ((given & (1 << reg)) != 0)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
started = 1;
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
}
|
||
|
||
if (domasklr)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
started = 1;
|
||
func (stream, arm_regnames[14] /* "lr" */);
|
||
}
|
||
|
||
if (domaskpc)
|
||
{
|
||
if (started)
|
||
func (stream, ", ");
|
||
func (stream, arm_regnames[15] /* "pc" */);
|
||
}
|
||
|
||
func (stream, "}");
|
||
}
|
||
break;
|
||
|
||
|
||
case '0': case '1': case '2': case '3': case '4':
|
||
case '5': case '6': case '7': case '8': case '9':
|
||
{
|
||
int bitstart = *c++ - '0';
|
||
int bitend = 0;
|
||
|
||
while (*c >= '0' && *c <= '9')
|
||
bitstart = (bitstart * 10) + *c++ - '0';
|
||
|
||
switch (*c)
|
||
{
|
||
case '-':
|
||
{
|
||
long reg;
|
||
|
||
c++;
|
||
while (*c >= '0' && *c <= '9')
|
||
bitend = (bitend * 10) + *c++ - '0';
|
||
if (!bitend)
|
||
abort ();
|
||
reg = given >> bitstart;
|
||
reg &= (2 << (bitend - bitstart)) - 1;
|
||
switch (*c)
|
||
{
|
||
case 'r':
|
||
func (stream, "%s", arm_regnames[reg]);
|
||
break;
|
||
|
||
case 'd':
|
||
func (stream, "%d", reg);
|
||
break;
|
||
|
||
case 'H':
|
||
func (stream, "%d", reg << 1);
|
||
break;
|
||
|
||
case 'W':
|
||
func (stream, "%d", reg << 2);
|
||
break;
|
||
|
||
case 'a':
|
||
/* PC-relative address -- the bottom two
|
||
bits of the address are dropped
|
||
before the calculation. */
|
||
info->print_address_func
|
||
(((pc + 4) & ~3) + (reg << 2), info);
|
||
break;
|
||
|
||
case 'x':
|
||
func (stream, "0x%04x", reg);
|
||
break;
|
||
|
||
case 'I':
|
||
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
||
func (stream, "%d", reg);
|
||
break;
|
||
|
||
case 'B':
|
||
reg = ((reg ^ (1 << bitend)) - (1 << bitend));
|
||
(*info->print_address_func)
|
||
(reg * 2 + pc + 4, info);
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
break;
|
||
|
||
case '\'':
|
||
c++;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c);
|
||
break;
|
||
|
||
case '?':
|
||
++c;
|
||
if ((given & (1 << bitstart)) != 0)
|
||
func (stream, "%c", *c++);
|
||
else
|
||
func (stream, "%c", *++c);
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
break;
|
||
|
||
default:
|
||
abort ();
|
||
}
|
||
}
|
||
else
|
||
func (stream, "%c", *c);
|
||
}
|
||
}
|
||
return 2;
|
||
}
|
||
}
|
||
|
||
/* No match. */
|
||
abort ();
|
||
}
|
||
|
||
/* Parse an individual disassembler option. */
|
||
void
|
||
parse_arm_disassembler_option (option)
|
||
char * option;
|
||
{
|
||
if (option == NULL)
|
||
return;
|
||
|
||
if (strneq (option, "reg-names-", 10))
|
||
{
|
||
int i;
|
||
|
||
option += 10;
|
||
|
||
for (i = NUM_ARM_REGNAMES; i--;)
|
||
if (streq (option, regnames[i].name))
|
||
{
|
||
regname_selected = i;
|
||
break;
|
||
}
|
||
|
||
if (i < 0)
|
||
fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
|
||
}
|
||
else if (streq (option, "force-thumb"))
|
||
force_thumb = 1;
|
||
else if (streq (option, "no-force-thumb"))
|
||
force_thumb = 0;
|
||
else
|
||
fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
|
||
|
||
return;
|
||
}
|
||
|
||
/* Parse the string of disassembler options, spliting it at whitespaces. */
|
||
static void
|
||
parse_disassembler_options (options)
|
||
char * options;
|
||
{
|
||
char * space;
|
||
|
||
if (options == NULL)
|
||
return;
|
||
|
||
do
|
||
{
|
||
space = strchr (options, ' ');
|
||
|
||
if (space)
|
||
{
|
||
* space = '\0';
|
||
parse_arm_disassembler_option (options);
|
||
* space = ' ';
|
||
options = space + 1;
|
||
}
|
||
else
|
||
parse_arm_disassembler_option (options);
|
||
}
|
||
while (space);
|
||
}
|
||
|
||
/* NOTE: There are no checks in these routines that
|
||
the relevant number of data bytes exist. */
|
||
static int
|
||
print_insn (pc, info, little)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
boolean little;
|
||
{
|
||
unsigned char b[4];
|
||
long given;
|
||
int status;
|
||
int is_thumb;
|
||
|
||
if (info->disassembler_options)
|
||
{
|
||
parse_disassembler_options (info->disassembler_options);
|
||
|
||
/* To avoid repeated parsing of these options, we remove them here. */
|
||
info->disassembler_options = NULL;
|
||
}
|
||
|
||
is_thumb = force_thumb;
|
||
|
||
if (!is_thumb && info->symbols != NULL)
|
||
{
|
||
if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
||
{
|
||
coff_symbol_type * cs;
|
||
|
||
cs = coffsymbol (*info->symbols);
|
||
is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
||
|| cs->native->u.syment.n_sclass == C_THUMBSTAT
|
||
|| cs->native->u.syment.n_sclass == C_THUMBLABEL
|
||
|| cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
||
|| cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
||
}
|
||
else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour)
|
||
{
|
||
elf_symbol_type * es;
|
||
unsigned int type;
|
||
|
||
es = *(elf_symbol_type **)(info->symbols);
|
||
type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
||
|
||
is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
|
||
}
|
||
}
|
||
|
||
info->bytes_per_chunk = 4;
|
||
info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
|
||
|
||
if (little)
|
||
{
|
||
status = info->read_memory_func (pc, (bfd_byte *) &b[0], 4, info);
|
||
if (status != 0 && is_thumb)
|
||
{
|
||
info->bytes_per_chunk = 2;
|
||
|
||
status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
|
||
b[3] = b[2] = 0;
|
||
}
|
||
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
|
||
}
|
||
else
|
||
{
|
||
status = info->read_memory_func
|
||
(pc & ~ 0x3, (bfd_byte *) &b[0], 4, info);
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc, info);
|
||
return -1;
|
||
}
|
||
|
||
if (is_thumb)
|
||
{
|
||
if (pc & 0x2)
|
||
{
|
||
given = (b[2] << 8) | b[3];
|
||
|
||
status = info->read_memory_func
|
||
((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info);
|
||
if (status != 0)
|
||
{
|
||
info->memory_error_func (status, pc + 4, info);
|
||
return -1;
|
||
}
|
||
|
||
given |= (b[0] << 24) | (b[1] << 16);
|
||
}
|
||
else
|
||
given = (b[0] << 8) | b[1] | (b[2] << 24) | (b[3] << 16);
|
||
}
|
||
else
|
||
given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
|
||
}
|
||
|
||
if (info->flags & INSN_HAS_RELOC)
|
||
/* If the instruction has a reloc associated with it, then
|
||
the offset field in the instruction will actually be the
|
||
addend for the reloc. (We are using REL type relocs).
|
||
In such cases, we can ignore the pc when computing
|
||
addresses, since the addend is not currently pc-relative. */
|
||
pc = 0;
|
||
|
||
if (is_thumb)
|
||
status = print_insn_thumb (pc, info, given);
|
||
else
|
||
status = print_insn_arm (pc, info, given);
|
||
|
||
return status;
|
||
}
|
||
|
||
int
|
||
print_insn_big_arm (pc, info)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
{
|
||
return print_insn (pc, info, false);
|
||
}
|
||
|
||
int
|
||
print_insn_little_arm (pc, info)
|
||
bfd_vma pc;
|
||
struct disassemble_info * info;
|
||
{
|
||
return print_insn (pc, info, true);
|
||
}
|
||
|
||
void
|
||
print_arm_disassembler_options (FILE * stream)
|
||
{
|
||
int i;
|
||
|
||
fprintf (stream, _("\n\
|
||
The following ARM specific disassembler options are supported for use with\n\
|
||
the -M switch:\n"));
|
||
|
||
for (i = NUM_ARM_REGNAMES; i--;)
|
||
fprintf (stream, " reg-names-%s %*c%s\n",
|
||
regnames[i].name,
|
||
(int)(14 - strlen (regnames[i].name)), ' ',
|
||
regnames[i].description);
|
||
|
||
fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
|
||
fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
|
||
}
|