mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
124 lines
4.3 KiB
C++
124 lines
4.3 KiB
C++
/* Common code for x86 XSAVE extended state.
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Copyright (C) 2010-2024 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef COMMON_X86_XSTATE_H
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#define COMMON_X86_XSTATE_H
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/* The extended state feature IDs in the state component bitmap. */
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#define X86_XSTATE_X87_ID 0
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#define X86_XSTATE_SSE_ID 1
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#define X86_XSTATE_AVX_ID 2
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#define X86_XSTATE_BNDREGS_ID 3
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#define X86_XSTATE_BNDCFG_ID 4
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#define X86_XSTATE_K_ID 5
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#define X86_XSTATE_ZMM_H_ID 6
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#define X86_XSTATE_ZMM_ID 7
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#define X86_XSTATE_PKRU_ID 9
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/* The extended state feature bits. */
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#define X86_XSTATE_X87 (1ULL << X86_XSTATE_X87_ID)
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#define X86_XSTATE_SSE (1ULL << X86_XSTATE_SSE_ID)
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#define X86_XSTATE_AVX (1ULL << X86_XSTATE_AVX_ID)
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#define X86_XSTATE_BNDREGS (1ULL << X86_XSTATE_BNDREGS_ID)
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#define X86_XSTATE_BNDCFG (1ULL << X86_XSTATE_BNDCFG_ID)
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#define X86_XSTATE_MPX (X86_XSTATE_BNDREGS | X86_XSTATE_BNDCFG)
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/* AVX 512 adds three feature bits. All three must be enabled. */
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#define X86_XSTATE_K (1ULL << X86_XSTATE_K_ID)
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#define X86_XSTATE_ZMM_H (1ULL << X86_XSTATE_ZMM_H_ID)
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#define X86_XSTATE_ZMM (1ULL << X86_XSTATE_ZMM_ID)
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#define X86_XSTATE_AVX512 (X86_XSTATE_K | X86_XSTATE_ZMM_H \
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| X86_XSTATE_ZMM)
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#define X86_XSTATE_PKRU (1ULL << X86_XSTATE_PKRU_ID)
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/* Total size of the XSAVE area extended region and offsets of
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register states within the region. Offsets are set to 0 to
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indicate the absence of the associated registers. */
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struct x86_xsave_layout
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{
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int sizeof_xsave = 0;
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int avx_offset = 0;
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int bndregs_offset = 0;
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int bndcfg_offset = 0;
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int k_offset = 0;
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int zmm_h_offset = 0;
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int zmm_offset = 0;
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int pkru_offset = 0;
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};
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constexpr bool operator== (const x86_xsave_layout &lhs,
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const x86_xsave_layout &rhs)
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{
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return lhs.sizeof_xsave == rhs.sizeof_xsave
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&& lhs.avx_offset == rhs.avx_offset
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&& lhs.bndregs_offset == rhs.bndregs_offset
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&& lhs.bndcfg_offset == rhs.bndcfg_offset
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&& lhs.k_offset == rhs.k_offset
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&& lhs.zmm_h_offset == rhs.zmm_h_offset
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&& lhs.zmm_offset == rhs.zmm_offset
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&& lhs.pkru_offset == rhs.pkru_offset;
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}
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constexpr bool operator!= (const x86_xsave_layout &lhs,
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const x86_xsave_layout &rhs)
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{
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return !(lhs == rhs);
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}
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/* Supported mask and size of the extended state. */
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#define X86_XSTATE_X87_MASK X86_XSTATE_X87
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#define X86_XSTATE_SSE_MASK (X86_XSTATE_X87 | X86_XSTATE_SSE)
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#define X86_XSTATE_AVX_MASK (X86_XSTATE_SSE_MASK | X86_XSTATE_AVX)
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#define X86_XSTATE_MPX_MASK (X86_XSTATE_SSE_MASK | X86_XSTATE_MPX)
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#define X86_XSTATE_AVX_MPX_MASK (X86_XSTATE_AVX_MASK | X86_XSTATE_MPX)
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#define X86_XSTATE_AVX_AVX512_MASK (X86_XSTATE_AVX_MASK | X86_XSTATE_AVX512)
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#define X86_XSTATE_AVX_MPX_AVX512_PKU_MASK (X86_XSTATE_AVX_MPX_MASK\
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| X86_XSTATE_AVX512 | X86_XSTATE_PKRU)
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#define X86_XSTATE_ALL_MASK (X86_XSTATE_AVX_MPX_AVX512_PKU_MASK)
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#define X86_XSTATE_SSE_SIZE 576
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#define X86_XSTATE_AVX_SIZE 832
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/* In case one of the MPX XCR0 bits is set we consider we have MPX. */
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#define HAS_MPX(XCR0) (((XCR0) & X86_XSTATE_MPX) != 0)
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#define HAS_AVX(XCR0) (((XCR0) & X86_XSTATE_AVX) != 0)
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#define HAS_AVX512(XCR0) (((XCR0) & X86_XSTATE_AVX512) != 0)
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#define HAS_PKRU(XCR0) (((XCR0) & X86_XSTATE_PKRU) != 0)
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/* Initial value for fctrl register, as defined in the X86 manual, and
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confirmed in the (Linux) kernel source. When the x87 floating point
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feature is not enabled in an inferior we use this as the value of the
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fcrtl register. */
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#define I387_FCTRL_INIT_VAL 0x037f
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/* Initial value for mxcsr register. When the avx and sse floating point
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features are not enabled in an inferior we use this as the value of the
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mxcsr register. */
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#define I387_MXCSR_INIT_VAL 0x1f80
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#endif /* COMMON_X86_XSTATE_H */
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