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https://sourceware.org/git/binutils-gdb.git
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fb53f5a81a
* All CGEN-generated sources: Regenerate.
Contribute the following changes:
2005-09-19 Dave Brolley <brolley@redhat.com>
* disassemble.c (disassemble_init_for_target): Add 'break' to case for
bfd_arch_tic4x. Use cgen_bitset_create and cgen_bitset_set for
bfd_arch_m32c case.
2005-02-16 Dave Brolley <brolley@redhat.com>
* cgen-dis.in: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
cgen_isa_mask_* to cgen_bitset_*.
* cgen-opc.c: Likewise.
2003-11-28 Richard Sandiford <rsandifo@redhat.com>
* cgen-dis.in (print_insn_@arch@): Fix comparison with cached isas.
* *-dis.c: Regenerate.
2003-06-05 DJ Delorie <dj@redhat.com>
* cgen-dis.in (print_insn_@arch@): Copy prev_isas, don't assign
it, as it may point to a reused buffer. Set prev_isas when we
change cpus.
2002-12-13 Dave Brolley <brolley@redhat.com>
* cgen-opc.c (cgen_isa_mask_create): New support function for
CGEN_ISA_MASK.
(cgen_isa_mask_init): Ditto.
(cgen_isa_mask_clear): Ditto.
(cgen_isa_mask_add): Ditto.
(cgen_isa_mask_set): Ditto.
(cgen_isa_supported): Ditto.
(cgen_isa_mask_compare): Ditto.
(cgen_isa_mask_intersection): Ditto.
(cgen_isa_mask_copy): Ditto.
(cgen_isa_mask_combine): Ditto.
* cgen-dis.in (libiberty.h): #include it.
(isas): Renamed from 'isa' and now (CGEN_ISA_MASK *).
(print_insn_@arch@): Use CGEN_ISA_MASK and support functions.
* Makefile.am (CGENDEPS): Add utils-cgen.scm and attrs.scm.
* Makefile.in: Regenerated.
319 lines
13 KiB
C
319 lines
13 KiB
C
/* CPU data header for fr30.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2005 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef FR30_CPU_H
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#define FR30_CPU_H
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#include "opcode/cgen-bitset.h"
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#define CGEN_ARCH fr30
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/* Given symbol S, return fr30_cgen_<S>. */
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#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
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#define CGEN_SYM(s) fr30##_cgen_##s
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#else
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#define CGEN_SYM(s) fr30/**/_cgen_/**/s
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#endif
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/* Selected cpu families. */
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#define HAVE_CPU_FR30BF
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#define CGEN_INSN_LSB0_P 0
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/* Minimum size of any insn (in bytes). */
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#define CGEN_MIN_INSN_SIZE 2
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/* Maximum size of any insn (in bytes). */
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#define CGEN_MAX_INSN_SIZE 6
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#define CGEN_INT_INSN_P 0
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/* Maximum number of syntax elements in an instruction. */
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#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
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/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
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e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
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we can't hash on everything up to the space. */
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#define CGEN_MNEMONIC_OPERANDS
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/* Maximum number of fields in an instruction. */
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#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
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/* Enums. */
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/* Enum declaration for insn op1 enums. */
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typedef enum insn_op1 {
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OP1_0, OP1_1, OP1_2, OP1_3
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, OP1_4, OP1_5, OP1_6, OP1_7
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, OP1_8, OP1_9, OP1_A, OP1_B
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, OP1_C, OP1_D, OP1_E, OP1_F
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} INSN_OP1;
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/* Enum declaration for insn op2 enums. */
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typedef enum insn_op2 {
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OP2_0, OP2_1, OP2_2, OP2_3
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, OP2_4, OP2_5, OP2_6, OP2_7
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, OP2_8, OP2_9, OP2_A, OP2_B
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, OP2_C, OP2_D, OP2_E, OP2_F
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} INSN_OP2;
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/* Enum declaration for insn op3 enums. */
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typedef enum insn_op3 {
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OP3_0, OP3_1, OP3_2, OP3_3
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, OP3_4, OP3_5, OP3_6, OP3_7
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, OP3_8, OP3_9, OP3_A, OP3_B
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, OP3_C, OP3_D, OP3_E, OP3_F
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} INSN_OP3;
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/* Enum declaration for insn op4 enums. */
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typedef enum insn_op4 {
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OP4_0
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} INSN_OP4;
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/* Enum declaration for insn op5 enums. */
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typedef enum insn_op5 {
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OP5_0, OP5_1
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} INSN_OP5;
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/* Enum declaration for insn cc enums. */
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typedef enum insn_cc {
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CC_RA, CC_NO, CC_EQ, CC_NE
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, CC_C, CC_NC, CC_N, CC_P
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, CC_V, CC_NV, CC_LT, CC_GE
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, CC_LE, CC_GT, CC_LS, CC_HI
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} INSN_CC;
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/* Enum declaration for . */
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typedef enum gr_names {
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H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
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, H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
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, H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
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, H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
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, H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
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} GR_NAMES;
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/* Enum declaration for . */
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typedef enum cr_names {
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H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
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, H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
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, H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
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, H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
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} CR_NAMES;
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/* Enum declaration for . */
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typedef enum dr_names {
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H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
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, H_DR_MDH, H_DR_MDL
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} DR_NAMES;
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/* Attributes. */
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/* Enum declaration for machine type selection. */
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typedef enum mach_attr {
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MACH_BASE, MACH_FR30, MACH_MAX
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} MACH_ATTR;
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/* Enum declaration for instruction set selection. */
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typedef enum isa_attr {
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ISA_FR30, ISA_MAX
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} ISA_ATTR;
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/* Number of architecture variants. */
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#define MAX_ISAS 1
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#define MAX_MACHS ((int) MACH_MAX)
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/* Ifield support. */
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/* Ifield attribute indices. */
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/* Enum declaration for cgen_ifld attrs. */
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typedef enum cgen_ifld_attr {
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CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
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, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
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, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
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} CGEN_IFLD_ATTR;
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/* Number of non-boolean elements in cgen_ifld_attr. */
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#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
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/* cgen_ifld attribute accessor macros. */
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#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
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#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
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#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
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#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
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#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
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/* Enum declaration for fr30 ifield types. */
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typedef enum ifield_type {
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FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
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, FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
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, FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
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, FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
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, FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
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, FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
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, FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
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, FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
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, FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
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, FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
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, FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
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} IFIELD_TYPE;
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#define MAX_IFLD ((int) FR30_F_MAX)
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/* Hardware attribute indices. */
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/* Enum declaration for cgen_hw attrs. */
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typedef enum cgen_hw_attr {
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CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
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, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
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} CGEN_HW_ATTR;
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/* Number of non-boolean elements in cgen_hw_attr. */
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#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
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/* cgen_hw attribute accessor macros. */
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#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
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#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
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#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
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/* Enum declaration for fr30 hardware types. */
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typedef enum cgen_hw_type {
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HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
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, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
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, HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
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, HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
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, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
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, HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
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, HW_H_ILM, HW_MAX
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} CGEN_HW_TYPE;
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#define MAX_HW ((int) HW_MAX)
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/* Operand attribute indices. */
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/* Enum declaration for cgen_operand attrs. */
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typedef enum cgen_operand_attr {
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CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
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, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
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, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
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, CGEN_OPERAND_END_NBOOLS
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} CGEN_OPERAND_ATTR;
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/* Number of non-boolean elements in cgen_operand_attr. */
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#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
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/* cgen_operand attribute accessor macros. */
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#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
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#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
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/* Enum declaration for fr30 operand types. */
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typedef enum cgen_operand_type {
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FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
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, FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
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, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
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, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
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, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
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, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
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, FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
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, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
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, FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
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, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
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, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
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, FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
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, FR30_OPERAND_ILM, FR30_OPERAND_MAX
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} CGEN_OPERAND_TYPE;
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/* Number of operands types. */
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#define MAX_OPERANDS 49
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/* Maximum number of operands referenced by any insn. */
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#define MAX_OPERAND_INSTANCES 8
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/* Insn attribute indices. */
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/* Enum declaration for cgen_insn attrs. */
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typedef enum cgen_insn_attr {
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CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
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, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
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, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
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, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
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} CGEN_INSN_ATTR;
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/* Number of non-boolean elements in cgen_insn_attr. */
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#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
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/* cgen_insn attribute accessor macros. */
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#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
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#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
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#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
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#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
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#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
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#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
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#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
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#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
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#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
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#define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
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/* cgen.h uses things we just defined. */
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#include "opcode/cgen.h"
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extern const struct cgen_ifld fr30_cgen_ifld_table[];
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/* Attributes. */
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extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
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extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
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extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
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extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
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/* Hardware decls. */
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extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
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extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
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extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
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extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
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extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
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extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
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extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
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extern const CGEN_HW_ENTRY fr30_cgen_hw_table[];
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#endif /* FR30_CPU_H */
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