mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-27 12:03:41 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
1053 lines
27 KiB
C
1053 lines
27 KiB
C
/* CPU family header for m32rxf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#ifndef CPU_M32RXF_H
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#define CPU_M32RXF_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 2
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 2
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/* The size of an "int" needed to hold an instruction word.
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This is usually 32 bits, but some architectures needs 64 bits. */
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typedef CGEN_INSN_INT CGEN_INSN_WORD;
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#include "cgen-engine.h"
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* general registers */
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SI h_gr[16];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* control registers */
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USI h_cr[16];
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#define GET_H_CR(index) m32rxf_h_cr_get_handler (current_cpu, index)
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#define SET_H_CR(index, x) \
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do { \
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m32rxf_h_cr_set_handler (current_cpu, (index), (x));\
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;} while (0)
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/* accumulator */
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DI h_accum;
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#define GET_H_ACCUM() m32rxf_h_accum_get_handler (current_cpu)
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#define SET_H_ACCUM(x) \
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do { \
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m32rxf_h_accum_set_handler (current_cpu, (x));\
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;} while (0)
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/* accumulators */
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DI h_accums[2];
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#define GET_H_ACCUMS(index) m32rxf_h_accums_get_handler (current_cpu, index)
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#define SET_H_ACCUMS(index, x) \
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do { \
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m32rxf_h_accums_set_handler (current_cpu, (index), (x));\
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;} while (0)
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/* condition bit */
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BI h_cond;
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#define GET_H_COND() CPU (h_cond)
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#define SET_H_COND(x) (CPU (h_cond) = (x))
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/* psw part of psw */
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UQI h_psw;
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#define GET_H_PSW() m32rxf_h_psw_get_handler (current_cpu)
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#define SET_H_PSW(x) \
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do { \
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m32rxf_h_psw_set_handler (current_cpu, (x));\
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;} while (0)
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/* backup psw */
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UQI h_bpsw;
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#define GET_H_BPSW() CPU (h_bpsw)
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#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
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/* backup bpsw */
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UQI h_bbpsw;
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#define GET_H_BBPSW() CPU (h_bbpsw)
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#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
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/* lock */
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BI h_lock;
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#define GET_H_LOCK() CPU (h_lock)
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#define SET_H_LOCK(x) (CPU (h_lock) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& M32R_SIM_CPU (cpu)->cpu_data.hardware)
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} M32RXF_CPU_DATA;
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/* Cover fns for register access. */
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USI m32rxf_h_pc_get (SIM_CPU *);
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void m32rxf_h_pc_set (SIM_CPU *, USI);
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SI m32rxf_h_gr_get (SIM_CPU *, UINT);
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void m32rxf_h_gr_set (SIM_CPU *, UINT, SI);
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USI m32rxf_h_cr_get (SIM_CPU *, UINT);
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void m32rxf_h_cr_set (SIM_CPU *, UINT, USI);
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DI m32rxf_h_accum_get (SIM_CPU *);
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void m32rxf_h_accum_set (SIM_CPU *, DI);
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DI m32rxf_h_accums_get (SIM_CPU *, UINT);
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void m32rxf_h_accums_set (SIM_CPU *, UINT, DI);
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BI m32rxf_h_cond_get (SIM_CPU *);
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void m32rxf_h_cond_set (SIM_CPU *, BI);
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UQI m32rxf_h_psw_get (SIM_CPU *);
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void m32rxf_h_psw_set (SIM_CPU *, UQI);
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UQI m32rxf_h_bpsw_get (SIM_CPU *);
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void m32rxf_h_bpsw_set (SIM_CPU *, UQI);
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UQI m32rxf_h_bbpsw_get (SIM_CPU *);
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void m32rxf_h_bbpsw_set (SIM_CPU *, UQI);
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BI m32rxf_h_lock_get (SIM_CPU *);
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void m32rxf_h_lock_set (SIM_CPU *, BI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN m32rxf_fetch_register;
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extern CPUREG_STORE_FN m32rxf_store_register;
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typedef struct {
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int empty;
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} MODEL_M32RX_DATA;
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/* Instruction argument buffer. */
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union sem_fields {
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struct { /* no operands */
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int empty;
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} sfmt_empty;
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struct { /* */
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UINT f_uimm8;
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} sfmt_clrpsw;
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struct { /* */
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UINT f_uimm4;
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} sfmt_trap;
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struct { /* */
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IADDR i_disp24;
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unsigned char out_h_gr_SI_14;
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} sfmt_bl24;
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struct { /* */
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IADDR i_disp8;
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unsigned char out_h_gr_SI_14;
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} sfmt_bl8;
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struct { /* */
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SI f_imm1;
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UINT f_accd;
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UINT f_accs;
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} sfmt_rac_dsi;
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struct { /* */
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SI* i_dr;
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UINT f_hi16;
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UINT f_r1;
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unsigned char out_dr;
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} sfmt_seth;
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struct { /* */
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SI* i_src1;
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UINT f_accs;
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UINT f_r1;
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unsigned char in_src1;
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} sfmt_mvtachi_a;
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struct { /* */
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SI* i_dr;
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UINT f_accs;
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UINT f_r1;
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unsigned char out_dr;
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} sfmt_mvfachi_a;
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struct { /* */
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ADDR i_uimm24;
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SI* i_dr;
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UINT f_r1;
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unsigned char out_dr;
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} sfmt_ld24;
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struct { /* */
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SI* i_sr;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_h_gr_SI_14;
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} sfmt_jl;
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struct { /* */
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SI* i_sr;
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INT f_simm16;
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UINT f_r2;
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UINT f_uimm3;
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unsigned char in_sr;
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} sfmt_bset;
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struct { /* */
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SI* i_dr;
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UINT f_r1;
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UINT f_uimm5;
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unsigned char in_dr;
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unsigned char out_dr;
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} sfmt_slli;
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struct { /* */
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SI* i_dr;
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INT f_simm8;
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UINT f_r1;
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unsigned char in_dr;
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unsigned char out_dr;
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} sfmt_addi;
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struct { /* */
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SI* i_src1;
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SI* i_src2;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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unsigned char out_src2;
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} sfmt_st_plus;
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struct { /* */
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SI* i_src1;
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SI* i_src2;
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INT f_simm16;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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} sfmt_st_d;
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struct { /* */
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SI* i_src1;
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SI* i_src2;
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UINT f_acc;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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} sfmt_machi_a;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_dr;
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unsigned char out_sr;
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} sfmt_ld_plus;
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struct { /* */
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IADDR i_disp16;
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SI* i_src1;
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SI* i_src2;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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} sfmt_beq;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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UINT f_uimm16;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_and3;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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INT f_simm16;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_add3;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_dr;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_add;
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#if WITH_SCACHE_PBB
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/* Writeback handler. */
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struct {
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/* Pointer to argbuf entry for insn whose results need writing back. */
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const struct argbuf *abuf;
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} write;
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/* x-before handler */
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struct {
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/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
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int first_p;
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} before;
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/* x-after handler */
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struct {
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int empty;
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} after;
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/* This entry is used to terminate each pbb. */
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struct {
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/* Number of insns in pbb. */
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int insn_count;
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/* Next pbb to execute. */
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SCACHE *next;
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SCACHE *branch_target;
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} chain;
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#endif
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};
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* ??? Temporary hack for skip insns. */
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char skip_count;
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char unused;
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/* cpu specific data follows */
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union sem semantic;
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int written;
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union sem_fields fields;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_ADD_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_ADD3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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INT f_simm16; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_AND3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_IFMT_AND3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_OR3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_IFMT_OR3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_ADDI_VARS \
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UINT f_op1; \
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UINT f_r1; \
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INT f_simm8; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDI_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
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#define EXTRACT_IFMT_ADDV3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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INT f_simm16; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDV3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_BC8_VARS \
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UINT f_op1; \
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UINT f_r1; \
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SI f_disp8; \
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unsigned int length;
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#define EXTRACT_IFMT_BC8_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4)))); \
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#define EXTRACT_IFMT_BC24_VARS \
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UINT f_op1; \
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UINT f_r1; \
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SI f_disp24; \
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unsigned int length;
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#define EXTRACT_IFMT_BC24_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc)); \
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#define EXTRACT_IFMT_BEQ_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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SI f_disp16; \
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unsigned int length;
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#define EXTRACT_IFMT_BEQ_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
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#define EXTRACT_IFMT_BEQZ_VARS \
|
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
|
|
SI f_disp16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BEQZ_CODE \
|
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length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
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f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc)); \
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#define EXTRACT_IFMT_CMP_VARS \
|
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UINT f_op1; \
|
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UINT f_r1; \
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UINT f_op2; \
|
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UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CMP_CODE \
|
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length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_CMPI_VARS \
|
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UINT f_op1; \
|
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
|
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INT f_simm16; \
|
|
unsigned int length;
|
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#define EXTRACT_IFMT_CMPI_CODE \
|
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length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_CMPZ_VARS \
|
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UINT f_op1; \
|
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UINT f_r1; \
|
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UINT f_op2; \
|
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UINT f_r2; \
|
|
unsigned int length;
|
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#define EXTRACT_IFMT_CMPZ_CODE \
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length = 2; \
|
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_DIV_VARS \
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UINT f_op1; \
|
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
|
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INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_DIV_CODE \
|
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length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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|
|
|
#define EXTRACT_IFMT_JC_VARS \
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UINT f_op1; \
|
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UINT f_r1; \
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UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_JC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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|
|
|
#define EXTRACT_IFMT_LD24_VARS \
|
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UINT f_op1; \
|
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UINT f_r1; \
|
|
UINT f_uimm24; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LD24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
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|
|
|
#define EXTRACT_IFMT_LDI16_VARS \
|
|
UINT f_op1; \
|
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UINT f_r1; \
|
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UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDI16_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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|
|
|
#define EXTRACT_IFMT_MACHI_A_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_acc; \
|
|
UINT f_op23; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_acc = EXTRACT_MSB0_UINT (insn, 16, 8, 1); \
|
|
f_op23 = EXTRACT_MSB0_UINT (insn, 16, 9, 3); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_MVFACHI_A_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_op3; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVFACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
|
|
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
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|
|
|
#define EXTRACT_IFMT_MVFC_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVFC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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|
|
|
#define EXTRACT_IFMT_MVTACHI_A_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_op3; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVTACHI_A_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
|
|
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 14, 2); \
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|
|
|
#define EXTRACT_IFMT_MVTC_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVTC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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|
|
|
#define EXTRACT_IFMT_NOP_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_NOP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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|
|
|
#define EXTRACT_IFMT_RAC_DSI_VARS \
|
|
UINT f_op1; \
|
|
UINT f_accd; \
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|
UINT f_bits67; \
|
|
UINT f_op2; \
|
|
UINT f_accs; \
|
|
UINT f_bit14; \
|
|
SI f_imm1; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_RAC_DSI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_accd = EXTRACT_MSB0_UINT (insn, 16, 4, 2); \
|
|
f_bits67 = EXTRACT_MSB0_UINT (insn, 16, 6, 2); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_accs = EXTRACT_MSB0_UINT (insn, 16, 12, 2); \
|
|
f_bit14 = EXTRACT_MSB0_UINT (insn, 16, 14, 1); \
|
|
f_imm1 = ((EXTRACT_MSB0_UINT (insn, 16, 15, 1)) + (1)); \
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|
|
|
#define EXTRACT_IFMT_SETH_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_hi16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SETH_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
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|
|
|
#define EXTRACT_IFMT_SLLI_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_shift_op2; \
|
|
UINT f_uimm5; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SLLI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
|
|
f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
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|
|
|
#define EXTRACT_IFMT_ST_D_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_ST_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_TRAP_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_uimm4; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TRAP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_SATB_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_uimm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SATB_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_CLRPSW_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_uimm8; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CLRPSW_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
|
|
|
#define EXTRACT_IFMT_BSET_VARS \
|
|
UINT f_op1; \
|
|
UINT f_bit4; \
|
|
UINT f_uimm3; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BSET_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
|
|
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_BTST_VARS \
|
|
UINT f_op1; \
|
|
UINT f_bit4; \
|
|
UINT f_uimm3; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BTST_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
|
|
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
/* Queued output values of an instruction. */
|
|
|
|
struct parexec {
|
|
union {
|
|
struct { /* empty sformat for unspecified field list */
|
|
int empty;
|
|
} sfmt_empty;
|
|
struct { /* e.g. add $dr,$sr */
|
|
SI dr;
|
|
} sfmt_add;
|
|
struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
|
|
SI dr;
|
|
} sfmt_add3;
|
|
struct { /* e.g. and3 $dr,$sr,$uimm16 */
|
|
SI dr;
|
|
} sfmt_and3;
|
|
struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
|
|
SI dr;
|
|
} sfmt_or3;
|
|
struct { /* e.g. addi $dr,$simm8 */
|
|
SI dr;
|
|
} sfmt_addi;
|
|
struct { /* e.g. addv $dr,$sr */
|
|
BI condbit;
|
|
SI dr;
|
|
} sfmt_addv;
|
|
struct { /* e.g. addv3 $dr,$sr,$simm16 */
|
|
BI condbit;
|
|
SI dr;
|
|
} sfmt_addv3;
|
|
struct { /* e.g. addx $dr,$sr */
|
|
BI condbit;
|
|
SI dr;
|
|
} sfmt_addx;
|
|
struct { /* e.g. bc.s $disp8 */
|
|
USI pc;
|
|
} sfmt_bc8;
|
|
struct { /* e.g. bc.l $disp24 */
|
|
USI pc;
|
|
} sfmt_bc24;
|
|
struct { /* e.g. beq $src1,$src2,$disp16 */
|
|
USI pc;
|
|
} sfmt_beq;
|
|
struct { /* e.g. beqz $src2,$disp16 */
|
|
USI pc;
|
|
} sfmt_beqz;
|
|
struct { /* e.g. bl.s $disp8 */
|
|
SI h_gr_SI_14;
|
|
USI pc;
|
|
} sfmt_bl8;
|
|
struct { /* e.g. bl.l $disp24 */
|
|
SI h_gr_SI_14;
|
|
USI pc;
|
|
} sfmt_bl24;
|
|
struct { /* e.g. bcl.s $disp8 */
|
|
SI h_gr_SI_14;
|
|
USI pc;
|
|
} sfmt_bcl8;
|
|
struct { /* e.g. bcl.l $disp24 */
|
|
SI h_gr_SI_14;
|
|
USI pc;
|
|
} sfmt_bcl24;
|
|
struct { /* e.g. bra.s $disp8 */
|
|
USI pc;
|
|
} sfmt_bra8;
|
|
struct { /* e.g. bra.l $disp24 */
|
|
USI pc;
|
|
} sfmt_bra24;
|
|
struct { /* e.g. cmp $src1,$src2 */
|
|
BI condbit;
|
|
} sfmt_cmp;
|
|
struct { /* e.g. cmpi $src2,$simm16 */
|
|
BI condbit;
|
|
} sfmt_cmpi;
|
|
struct { /* e.g. cmpz $src2 */
|
|
BI condbit;
|
|
} sfmt_cmpz;
|
|
struct { /* e.g. div $dr,$sr */
|
|
SI dr;
|
|
} sfmt_div;
|
|
struct { /* e.g. jc $sr */
|
|
USI pc;
|
|
} sfmt_jc;
|
|
struct { /* e.g. jl $sr */
|
|
SI h_gr_SI_14;
|
|
USI pc;
|
|
} sfmt_jl;
|
|
struct { /* e.g. jmp $sr */
|
|
USI pc;
|
|
} sfmt_jmp;
|
|
struct { /* e.g. ld $dr,@$sr */
|
|
SI dr;
|
|
} sfmt_ld;
|
|
struct { /* e.g. ld $dr,@($slo16,$sr) */
|
|
SI dr;
|
|
} sfmt_ld_d;
|
|
struct { /* e.g. ldb $dr,@$sr */
|
|
SI dr;
|
|
} sfmt_ldb;
|
|
struct { /* e.g. ldb $dr,@($slo16,$sr) */
|
|
SI dr;
|
|
} sfmt_ldb_d;
|
|
struct { /* e.g. ldh $dr,@$sr */
|
|
SI dr;
|
|
} sfmt_ldh;
|
|
struct { /* e.g. ldh $dr,@($slo16,$sr) */
|
|
SI dr;
|
|
} sfmt_ldh_d;
|
|
struct { /* e.g. ld $dr,@$sr+ */
|
|
SI dr;
|
|
SI sr;
|
|
} sfmt_ld_plus;
|
|
struct { /* e.g. ld24 $dr,$uimm24 */
|
|
SI dr;
|
|
} sfmt_ld24;
|
|
struct { /* e.g. ldi8 $dr,$simm8 */
|
|
SI dr;
|
|
} sfmt_ldi8;
|
|
struct { /* e.g. ldi16 $dr,$hash$slo16 */
|
|
SI dr;
|
|
} sfmt_ldi16;
|
|
struct { /* e.g. lock $dr,@$sr */
|
|
SI dr;
|
|
BI h_lock_BI;
|
|
} sfmt_lock;
|
|
struct { /* e.g. machi $src1,$src2,$acc */
|
|
DI acc;
|
|
} sfmt_machi_a;
|
|
struct { /* e.g. mulhi $src1,$src2,$acc */
|
|
DI acc;
|
|
} sfmt_mulhi_a;
|
|
struct { /* e.g. mv $dr,$sr */
|
|
SI dr;
|
|
} sfmt_mv;
|
|
struct { /* e.g. mvfachi $dr,$accs */
|
|
SI dr;
|
|
} sfmt_mvfachi_a;
|
|
struct { /* e.g. mvfc $dr,$scr */
|
|
SI dr;
|
|
} sfmt_mvfc;
|
|
struct { /* e.g. mvtachi $src1,$accs */
|
|
DI accs;
|
|
} sfmt_mvtachi_a;
|
|
struct { /* e.g. mvtc $sr,$dcr */
|
|
USI dcr;
|
|
} sfmt_mvtc;
|
|
struct { /* e.g. nop */
|
|
int empty;
|
|
} sfmt_nop;
|
|
struct { /* e.g. rac $accd,$accs,$imm1 */
|
|
DI accd;
|
|
} sfmt_rac_dsi;
|
|
struct { /* e.g. rte */
|
|
UQI h_bpsw_UQI;
|
|
USI h_cr_USI_6;
|
|
UQI h_psw_UQI;
|
|
USI pc;
|
|
} sfmt_rte;
|
|
struct { /* e.g. seth $dr,$hash$hi16 */
|
|
SI dr;
|
|
} sfmt_seth;
|
|
struct { /* e.g. sll3 $dr,$sr,$simm16 */
|
|
SI dr;
|
|
} sfmt_sll3;
|
|
struct { /* e.g. slli $dr,$uimm5 */
|
|
SI dr;
|
|
} sfmt_slli;
|
|
struct { /* e.g. st $src1,@$src2 */
|
|
SI h_memory_SI_src2;
|
|
USI h_memory_SI_src2_idx;
|
|
} sfmt_st;
|
|
struct { /* e.g. st $src1,@($slo16,$src2) */
|
|
SI h_memory_SI_add__SI_src2_slo16;
|
|
USI h_memory_SI_add__SI_src2_slo16_idx;
|
|
} sfmt_st_d;
|
|
struct { /* e.g. stb $src1,@$src2 */
|
|
QI h_memory_QI_src2;
|
|
USI h_memory_QI_src2_idx;
|
|
} sfmt_stb;
|
|
struct { /* e.g. stb $src1,@($slo16,$src2) */
|
|
QI h_memory_QI_add__SI_src2_slo16;
|
|
USI h_memory_QI_add__SI_src2_slo16_idx;
|
|
} sfmt_stb_d;
|
|
struct { /* e.g. sth $src1,@$src2 */
|
|
HI h_memory_HI_src2;
|
|
USI h_memory_HI_src2_idx;
|
|
} sfmt_sth;
|
|
struct { /* e.g. sth $src1,@($slo16,$src2) */
|
|
HI h_memory_HI_add__SI_src2_slo16;
|
|
USI h_memory_HI_add__SI_src2_slo16_idx;
|
|
} sfmt_sth_d;
|
|
struct { /* e.g. st $src1,@+$src2 */
|
|
SI h_memory_SI_new_src2;
|
|
USI h_memory_SI_new_src2_idx;
|
|
SI src2;
|
|
} sfmt_st_plus;
|
|
struct { /* e.g. sth $src1,@$src2+ */
|
|
HI h_memory_HI_new_src2;
|
|
USI h_memory_HI_new_src2_idx;
|
|
SI src2;
|
|
} sfmt_sth_plus;
|
|
struct { /* e.g. stb $src1,@$src2+ */
|
|
QI h_memory_QI_new_src2;
|
|
USI h_memory_QI_new_src2_idx;
|
|
SI src2;
|
|
} sfmt_stb_plus;
|
|
struct { /* e.g. trap $uimm4 */
|
|
UQI h_bbpsw_UQI;
|
|
UQI h_bpsw_UQI;
|
|
USI h_cr_USI_14;
|
|
USI h_cr_USI_6;
|
|
UQI h_psw_UQI;
|
|
USI pc;
|
|
} sfmt_trap;
|
|
struct { /* e.g. unlock $src1,@$src2 */
|
|
BI h_lock_BI;
|
|
SI h_memory_SI_src2;
|
|
USI h_memory_SI_src2_idx;
|
|
} sfmt_unlock;
|
|
struct { /* e.g. satb $dr,$sr */
|
|
SI dr;
|
|
} sfmt_satb;
|
|
struct { /* e.g. sat $dr,$sr */
|
|
SI dr;
|
|
} sfmt_sat;
|
|
struct { /* e.g. sadd */
|
|
DI h_accums_DI_0;
|
|
} sfmt_sadd;
|
|
struct { /* e.g. macwu1 $src1,$src2 */
|
|
DI h_accums_DI_1;
|
|
} sfmt_macwu1;
|
|
struct { /* e.g. msblo $src1,$src2 */
|
|
DI accum;
|
|
} sfmt_msblo;
|
|
struct { /* e.g. mulwu1 $src1,$src2 */
|
|
DI h_accums_DI_1;
|
|
} sfmt_mulwu1;
|
|
struct { /* e.g. sc */
|
|
int empty;
|
|
} sfmt_sc;
|
|
struct { /* e.g. clrpsw $uimm8 */
|
|
USI h_cr_USI_0;
|
|
} sfmt_clrpsw;
|
|
struct { /* e.g. setpsw $uimm8 */
|
|
USI h_cr_USI_0;
|
|
} sfmt_setpsw;
|
|
struct { /* e.g. bset $uimm3,@($slo16,$sr) */
|
|
QI h_memory_QI_add__SI_sr_slo16;
|
|
USI h_memory_QI_add__SI_sr_slo16_idx;
|
|
} sfmt_bset;
|
|
struct { /* e.g. btst $uimm3,$sr */
|
|
BI condbit;
|
|
} sfmt_btst;
|
|
} operands;
|
|
/* For conditionally written operands, bitmask of which ones were. */
|
|
int written;
|
|
};
|
|
|
|
/* Collection of various things for the trace handler to use. */
|
|
|
|
typedef struct trace_record {
|
|
IADDR pc;
|
|
/* FIXME:wip */
|
|
} TRACE_RECORD;
|
|
|
|
#endif /* CPU_M32RXF_H */
|