Richard Henderson 07f5f4c683 or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns ... Also fix the incorrect definitions of multiply and divide carry and overflow float. Changes to the instructions are made in the .cpu file, then we regenerate the binutils and sim files. The changes also required a few fixups for tests and additional sim helpers. cpu/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1korbis.cpu (insn-opcode-mac): Add opcodes for MACU and MSBU. (insn-opcode-alu-regreg): Add opcodes for MULD and MULDU. (l-mul): Fix overflow support and indentation. (l-mulu): Fix overflow support and indentation. (l-muld, l-muldu, l-msbu, l-macu): New instructions. (l-div); Remove incorrect carry behavior. (l-divu): Fix carry and overflow behavior. (l-mac): Add overflow support. (l-msb, l-msbu): Add carry and overflow support. opcodes/ChangeLog: yyyy-mm-dd Richard Henderson <rth@twiddle.net> Stafford Horne <shorne@gmail.com> * or1k-desc.c: Regenerate. * or1k-desc.h: Regenerate. * or1k-opc.c: Regenerate. * or1k-opc.h: Regenerate. * or1k-opinst.c: Regenerate. sim/common/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * cgen-ops.h (ADDCFDI): New function, add carry flag DI variant. (ADDOFDI): New function, add overflow flag DI variant. (SUBCFDI): New function, subtract carry flag DI variant. (SUBOFDI): New function, subtract overflow flag DI variant. sim/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * or1k/cpu.h: Regenerate. * or1k/decode.c: Regenerate. * or1k/decode.h: Regenerate. * or1k/model.c: Regenerate. * or1k/sem-switch.c: Regenerate. * or1k/sem.c: Regenerate: sim/testsuite/sim/or1k/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * div.S: Fix tests to match correct overflow/carry semantics. * mul.S: Likewise. gas/ChangeLog: yyyy-mm-dd Stafford Horne <shorne@gmail.com> * testsuite/gas/or1k/allinsn.s: Add instruction tests for l.muld, l.muldu, l.macu, l.msb, l.msbu. * testsuite/gas/or1k/allinsn.d: Add test results for new instructions.		2018-10-05 11:41:42 +09:00
..
ChangeLog	or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns	2018-10-05 11:41:42 +09:00
cris.cpu
epiphany.cpu	2012-11-30 Oleg Raikhman <oleg@adapteva.com>	2012-11-30 17:54:58 +00:00
epiphany.opc	epiphany/disassembler: Improve alignment of output.	2016-02-02 11:09:17 +00:00
fr30.cpu	Correct fr30 comment	2016-03-03 12:55:30 +10:30
fr30.opc
frv.cpu
frv.opc	opcodes error messages	2018-03-03 11:34:26 +10:30
ip2k.cpu
ip2k.opc
iq10.cpu
iq2000.cpu
iq2000.opc
iq2000m.cpu
lm32.cpu	PR binutils/15241	2013-03-08 17:25:12 +00:00
lm32.opc
m32c.cpu
m32c.opc
m32r.cpu
m32r.opc
mep-avc2.cpu
mep-avc.cpu
mep-c5.cpu
mep-core.cpu
mep-default.cpu
mep-ext-cop.cpu
mep-fmax.cpu
mep-h1.cpu
mep-ivc2.cpu
mep-rhcop.cpu
mep-sample-ucidsp.cpu
mep.cpu
mep.opc	Add fall through comment to source in cpu/	2016-10-06 22:48:37 +10:30
mt.cpu
mt.opc
or1k.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
or1k.opc	or1k: Add the l.adrp insn and supporting relocations	2018-10-05 11:41:41 +09:00
or1kcommon.cpu	PR23430, Indices misspelled	2018-07-24 19:58:12 +09:30
or1korbis.cpu	or1k: Add the l.muld, l.muldu, l.macu, l.msbu insns	2018-10-05 11:41:42 +09:00
or1korfpx.cpu	Remove support for the (deprecated) openrisc and or32 configurations and replace	2014-04-22 15:57:47 +01:00
sh64-compact.cpu
sh64-media.cpu
sh.cpu
sh.opc
simplify.inc
xc16x.cpu
xc16x.opc
xstormy16.cpu
xstormy16.opc