Mike Frysinger d16ce6e4d5 sim: cris: fix memory setup typos ... The cleanup to use BFD_VMA_FMT also adjusted this line, but used the incorrect format: while BFD_VMA_FMT needs an explicit "x", PRIx32 does not, so the spurious "x" here confused the parser and broke execution.		2021-05-23 23:43:37 -04:00
..
aarch64	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
arm	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
avr	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
bfin	sim: bfin: fix the otp fix	2021-05-23 22:16:13 -04:00
bpf	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
common	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
cr16	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
cris	sim: cris: fix memory setup typos	2021-05-23 23:43:37 -04:00
d10v	sim/d10v: Use offsetof in a static assertion about structure layout.	2021-05-21 17:27:05 -07:00
erc32	sim: switch config.h usage to defs.h	2021-05-16 22:38:41 -04:00
example-synacor	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
frv	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
ft32	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
h8300	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
igen	sim: add support for build-time ar & ranlib	2021-05-04 08:22:07 -04:00
iq2000	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
lm32	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
m4	sim: riscv: move __int128 check to configure	2021-05-16 00:04:17 -04:00
m32c	sim: switch config.h usage to defs.h	2021-05-16 22:38:41 -04:00
m32r	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
m68hc11	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
mcore	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
microblaze	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
mips	sim: mips: Add shadow mappings for 32-bit memory address space	2021-05-22 11:32:35 +05:30
mn10300	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
moxie	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
msp430	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
or1k	sim: cgen: invert sim_state storage for cgen ports	2021-05-17 00:46:32 -04:00
ppc	sim: ppc: fix Wpointer-sign warning	2021-05-20 13:58:35 +02:00
pru	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
riscv	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
rl78	sim: rl78: rename open symbol to avoid collisions	2021-05-23 17:40:32 -04:00
rx	sim: switch config.h usage to defs.h	2021-05-16 22:38:41 -04:00
sh	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
testsuite	sim: Add bfd include path for common testsuite tools	2021-05-07 21:02:34 +03:00
v850	sim: fully merge sim_state_base into sim_state	2021-05-17 01:05:08 -04:00
.gitignore	sim: drop common/cconfig.h in favor of a single config.h	2016-01-09 03:52:30 -05:00
aclocal.m4	sim: unify toolchain settings	2021-04-02 23:31:14 -04:00
ChangeLog	sim: install library header files	2021-05-16 22:42:02 -04:00
configure	sim: add support for build-time ar & ranlib	2021-05-04 08:22:07 -04:00
configure.ac	sim: example-synacor: a simple implementation for reference	2021-04-03 16:19:16 -04:00
MAINTAINERS	sim: readd myself as a maintainer	2021-01-29 22:11:45 -05:00
Makefile.am	sim: install library header files	2021-05-16 22:42:02 -04:00
Makefile.in	sim: install library header files	2021-05-16 22:42:02 -04:00
README-HACKING	sim: create header namespace	2021-05-14 00:41:05 -04:00