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https://sourceware.org/git/binutils-gdb.git
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d87bef3a7b
The newer update-copyright.py fixes file encoding too, removing cr/lf on binutils/bfdtest2.c and ld/testsuite/ld-cygwin/exe-export.exp, and embedded cr in binutils/testsuite/binutils-all/ar.exp string match.
2307 lines
50 KiB
C
2307 lines
50 KiB
C
/* This is the machine dependent code of the Visium Assembler.
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Copyright (C) 2005-2023 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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GAS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "as.h"
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#include "safe-ctype.h"
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#include "subsegs.h"
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#include "obstack.h"
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#include "opcode/visium.h"
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#include "elf/visium.h"
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#include "dwarf2dbg.h"
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#include "dw2gencfi.h"
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/* Relocations and fixups:
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There are two different cases where an instruction or data
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directive operand requires relocation, or fixup.
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1. Relative branch instructions, take an 16-bit signed word
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offset. The formula for computing the offset is this:
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offset = (destination - pc) / 4
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Branch instructions never branch to a label not declared
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locally, so the actual offset can always be computed by the assembler.
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However, we provide a relocation type to support this.
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2. Load literal instructions, such as MOVIU, which take a 16-bit
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literal operand. The literal may be the top or bottom half of
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a 32-bit value computed by the assembler, or by the linker. We provide
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two relocation types here.
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3. Data items (long, word and byte) preset with a value computed by
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the linker. */
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/* This string holds the chars that always start a comment. If the
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pre-processor is disabled, these aren't very useful. The macro
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tc_comment_chars points to this. */
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const char *visium_comment_chars = "!;";
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/* This array holds the chars that only start a comment at the beginning
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of a line. If the line seems to have the form '# 123 filename' .line
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and .file directives will appear in the pre-processed output. Note that
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input_file.c hand checks for '#' at the beginning of the first line of
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the input file. This is because the compiler outputs #NO_APP at the
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beginning of its output. Also note that comments like this one will
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always work. */
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const char line_comment_chars[] = "#!;";
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const char line_separator_chars[] = "";
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/* Chars that can be used to separate mantissa from exponent in floating point
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numbers. */
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const char EXP_CHARS[] = "eE";
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/* Chars that mean this number is a floating point constant, as in
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"0f12.456" or "0d1.2345e12".
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...Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be
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changed in read.c. Ideally it shouldn't have to know about it at all,
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but nothing is ideal around here. */
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const char FLT_CHARS[] = "rRsSfFdDxXeE";
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/* The size of a relocation record. */
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const int md_reloc_size = 8;
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/* The architecture for which we are assembling. */
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enum visium_arch_val
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{
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VISIUM_ARCH_DEF,
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VISIUM_ARCH_MCM24,
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VISIUM_ARCH_MCM,
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VISIUM_ARCH_GR6
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};
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static enum visium_arch_val visium_arch = VISIUM_ARCH_DEF;
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/* The opcode architecture for which we are assembling. In contrast to the
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previous one, this only determines which instructions are supported. */
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static enum visium_opcode_arch_val visium_opcode_arch = VISIUM_OPCODE_ARCH_DEF;
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/* Flags to set in the ELF header e_flags field. */
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static flagword visium_flags = 0;
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/* More than this number of nops in an alignment op gets a branch instead. */
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static unsigned int nop_limit = 5;
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/* Translate internal representation of relocation info to BFD target
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format. */
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arelent *
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tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
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{
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arelent *reloc;
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bfd_reloc_code_real_type code;
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reloc = XNEW (arelent);
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reloc->sym_ptr_ptr = XNEW (asymbol *);
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*reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
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reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
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switch (fixp->fx_r_type)
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{
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case BFD_RELOC_8:
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case BFD_RELOC_16:
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case BFD_RELOC_32:
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case BFD_RELOC_8_PCREL:
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case BFD_RELOC_16_PCREL:
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case BFD_RELOC_32_PCREL:
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case BFD_RELOC_VISIUM_HI16:
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case BFD_RELOC_VISIUM_LO16:
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case BFD_RELOC_VISIUM_IM16:
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case BFD_RELOC_VISIUM_REL16:
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case BFD_RELOC_VISIUM_HI16_PCREL:
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case BFD_RELOC_VISIUM_LO16_PCREL:
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case BFD_RELOC_VISIUM_IM16_PCREL:
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case BFD_RELOC_VTABLE_INHERIT:
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case BFD_RELOC_VTABLE_ENTRY:
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code = fixp->fx_r_type;
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break;
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default:
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as_bad_where (fixp->fx_file, fixp->fx_line,
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"internal error: unknown relocation type %d (`%s')",
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fixp->fx_r_type,
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bfd_get_reloc_code_name (fixp->fx_r_type));
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return 0;
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}
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reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
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if (reloc->howto == 0)
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{
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as_bad_where (fixp->fx_file, fixp->fx_line,
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"internal error: can't export reloc type %d (`%s')",
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fixp->fx_r_type, bfd_get_reloc_code_name (code));
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return 0;
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}
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/* Write the addend. */
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if (reloc->howto->pc_relative == 0)
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reloc->addend = fixp->fx_addnumber;
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else
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reloc->addend = fixp->fx_offset;
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return reloc;
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}
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extern char *input_line_pointer;
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static void s_bss (int);
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static void visium_rdata (int);
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static void visium_update_parity_bit (char *);
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static char *parse_exp (char *, expressionS *);
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/* These are the back-ends for the various machine dependent pseudo-ops. */
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void demand_empty_rest_of_line (void);
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static void
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s_bss (int ignore ATTRIBUTE_UNUSED)
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{
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/* We don't support putting frags in the BSS segment, we fake it
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by marking in_bss, then looking at s_skip for clues. */
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subseg_set (bss_section, 0);
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demand_empty_rest_of_line ();
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}
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/* This table describes all the machine specific pseudo-ops the assembler
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has to support. The fields are:
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1: Pseudo-op name without dot.
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2: Function to call to execute this pseudo-op.
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3: Integer arg to pass to the function. */
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const pseudo_typeS md_pseudo_table[] =
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{
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{"bss", s_bss, 0},
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{"skip", s_space, 0},
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{"align", s_align_bytes, 0},
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{"noopt", s_ignore, 0},
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{"optim", s_ignore, 0},
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{"rdata", visium_rdata, 0},
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{"rodata", visium_rdata, 0},
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{0, 0, 0}
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};
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static void
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visium_rdata (int xxx)
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{
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char *save_line = input_line_pointer;
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static char section[] = ".rodata\n";
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/* Just pretend this is .section .rodata */
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input_line_pointer = section;
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obj_elf_section (xxx);
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input_line_pointer = save_line;
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}
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/* Align a section. */
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valueT
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md_section_align (asection *seg, valueT addr)
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{
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int align = bfd_section_alignment (seg);
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return ((addr + (1 << align) - 1) & -(1 << align));
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}
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void
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md_number_to_chars (char *buf, valueT val, int n)
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{
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number_to_chars_bigendian (buf, val, n);
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}
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symbolS *
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md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
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{
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return 0;
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}
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/* The parse options. */
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const char *md_shortopts = "m:";
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struct option md_longopts[] =
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{
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof (md_longopts);
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struct visium_option_table
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{
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char *option; /* Option name to match. */
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char *help; /* Help information. */
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int *var; /* Variable to change. */
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int value; /* To what to change it. */
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char *deprecated; /* If non-null, print this message. */
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};
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static struct visium_option_table visium_opts[] =
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{
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{NULL, NULL, NULL, 0, NULL}
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};
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struct visium_arch_option_table
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{
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const char *name;
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enum visium_arch_val value;
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};
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static struct visium_arch_option_table visium_archs[] =
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{
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{"mcm24", VISIUM_ARCH_MCM24},
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{"mcm", VISIUM_ARCH_MCM},
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{"gr5", VISIUM_ARCH_MCM},
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{"gr6", VISIUM_ARCH_GR6},
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};
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struct visium_long_option_table
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{
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const char *option; /* Substring to match. */
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const char *help; /* Help information. */
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int (*func) (const char *subopt); /* Function to decode sub-option. */
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const char *deprecated; /* If non-null, print this message. */
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};
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static int
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visium_parse_arch (const char *str)
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{
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unsigned int i;
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if (strlen (str) == 0)
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{
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as_bad ("missing architecture name `%s'", str);
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return 0;
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}
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for (i = 0; i < ARRAY_SIZE (visium_archs); i++)
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if (strcmp (visium_archs[i].name, str) == 0)
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{
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visium_arch = visium_archs[i].value;
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return 1;
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}
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as_bad ("unknown architecture `%s'\n", str);
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return 0;
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}
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static struct visium_long_option_table visium_long_opts[] =
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{
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{"mtune=", "<arch_name>\t assemble for architecture <arch name>",
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visium_parse_arch, NULL},
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{NULL, NULL, NULL, NULL}
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};
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int
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md_parse_option (int c, const char *arg)
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{
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struct visium_option_table *opt;
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struct visium_long_option_table *lopt;
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switch (c)
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{
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case 'a':
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/* Listing option. Just ignore these, we don't support additional
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ones. */
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return 0;
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default:
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for (opt = visium_opts; opt->option != NULL; opt++)
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{
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if (c == opt->option[0]
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&& ((arg == NULL && opt->option[1] == 0)
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|| strcmp (arg, opt->option + 1) == 0))
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{
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/* If the option is deprecated, tell the user. */
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if (opt->deprecated != NULL)
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as_tsktsk ("option `-%c%s' is deprecated: %s", c,
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arg ? arg : "", opt->deprecated);
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if (opt->var != NULL)
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*opt->var = opt->value;
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return 1;
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}
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}
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for (lopt = visium_long_opts; lopt->option != NULL; lopt++)
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{
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/* These options are expected to have an argument. */
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if (c == lopt->option[0]
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&& arg != NULL
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&& strncmp (arg, lopt->option + 1,
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strlen (lopt->option + 1)) == 0)
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{
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/* If the option is deprecated, tell the user. */
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if (lopt->deprecated != NULL)
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as_tsktsk ("option `-%c%s' is deprecated: %s", c, arg,
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lopt->deprecated);
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/* Call the sup-option parser. */
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return lopt->func (arg + strlen (lopt->option) - 1);
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}
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}
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return 0;
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}
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return 1;
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}
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void
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md_show_usage (FILE * fp)
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{
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struct visium_option_table *opt;
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struct visium_long_option_table *lopt;
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fprintf (fp, " Visium-specific assembler options:\n");
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for (opt = visium_opts; opt->option != NULL; opt++)
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if (opt->help != NULL)
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fprintf (fp, " -%-23s%s\n", opt->option, opt->help);
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for (lopt = visium_long_opts; lopt->option != NULL; lopt++)
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if (lopt->help != NULL)
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fprintf (fp, " -%s%s\n", lopt->option, lopt->help);
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}
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/* Interface to relax_segment. */
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/* Return the estimate of the size of a machine dependent frag
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before any relaxing is done. It may also create any necessary
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relocations. */
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int
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md_estimate_size_before_relax (fragS * fragP,
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segT segment ATTRIBUTE_UNUSED)
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{
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fragP->fr_var = 4;
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return 4;
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}
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/* Get the address of a symbol during relaxation. From tc-arm.c. */
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static addressT
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relaxed_symbol_addr (fragS *fragp, long stretch)
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{
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fragS *sym_frag;
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addressT addr;
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symbolS *sym;
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sym = fragp->fr_symbol;
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sym_frag = symbol_get_frag (sym);
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know (S_GET_SEGMENT (sym) != absolute_section
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|| sym_frag == &zero_address_frag);
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addr = S_GET_VALUE (sym) + fragp->fr_offset;
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/* If frag has yet to be reached on this pass, assume it will
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move by STRETCH just as we did. If this is not so, it will
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be because some frag between grows, and that will force
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another pass. */
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if (stretch != 0
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&& sym_frag->relax_marker != fragp->relax_marker)
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{
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fragS *f;
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/* Adjust stretch for any alignment frag. Note that if have
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been expanding the earlier code, the symbol may be
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defined in what appears to be an earlier frag. FIXME:
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This doesn't handle the fr_subtype field, which specifies
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a maximum number of bytes to skip when doing an
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alignment. */
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for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
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{
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if (f->fr_type == rs_align || f->fr_type == rs_align_code)
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{
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if (stretch < 0)
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stretch = - ((- stretch)
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& ~ ((1 << (int) f->fr_offset) - 1));
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else
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stretch &= ~ ((1 << (int) f->fr_offset) - 1);
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if (stretch == 0)
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break;
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}
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}
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if (f != NULL)
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addr += stretch;
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}
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return addr;
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}
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/* Relax a machine dependent frag. This returns the amount by which
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the current size of the frag should change. */
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int
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visium_relax_frag (asection *sec, fragS *fragP, long stretch)
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{
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int old_size, new_size;
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addressT addr;
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/* We only handle relaxation for the BRR instruction. */
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gas_assert (fragP->fr_subtype == mode_ci);
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if (!S_IS_DEFINED (fragP->fr_symbol)
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|| sec != S_GET_SEGMENT (fragP->fr_symbol)
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|| S_IS_WEAK (fragP->fr_symbol))
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return 0;
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old_size = fragP->fr_var;
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addr = relaxed_symbol_addr (fragP, stretch);
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/* If the target is the address of the instruction, we'll insert a NOP. */
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if (addr == fragP->fr_address + fragP->fr_fix)
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new_size = 8;
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else
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new_size = 4;
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fragP->fr_var = new_size;
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return new_size - old_size;
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}
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/* Convert a machine dependent frag. */
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void
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md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
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fragS * fragP)
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{
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char *buf = &fragP->fr_literal[0] + fragP->fr_fix;
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expressionS exp;
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fixS *fixP;
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/* We only handle relaxation for the BRR instruction. */
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gas_assert (fragP->fr_subtype == mode_ci);
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/* Insert the NOP if requested. */
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if (fragP->fr_var == 8)
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{
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memcpy (buf + 4, buf, 4);
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memset (buf, 0, 4);
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fragP->fr_fix += 4;
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}
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exp.X_op = O_symbol;
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exp.X_add_symbol = fragP->fr_symbol;
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exp.X_add_number = fragP->fr_offset;
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/* Now we can create the relocation at the correct offset. */
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fixP = fix_new_exp (fragP, fragP->fr_fix, 4, &exp, 1, BFD_RELOC_VISIUM_REL16);
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fixP->fx_file = fragP->fr_file;
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fixP->fx_line = fragP->fr_line;
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fragP->fr_fix += 4;
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fragP->fr_var = 0;
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}
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/* The location from which a PC relative jump should be calculated,
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given a PC relative jump reloc. */
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long
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visium_pcrel_from_section (fixS *fixP, segT sec)
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{
|
|
if (fixP->fx_addsy != (symbolS *) NULL
|
|
&& (!S_IS_DEFINED (fixP->fx_addsy)
|
|
|| S_GET_SEGMENT (fixP->fx_addsy) != sec))
|
|
{
|
|
/* The symbol is undefined (or is defined but not in this section).
|
|
Let the linker figure it out. */
|
|
return 0;
|
|
}
|
|
|
|
/* Return the address of the instruction. */
|
|
return fixP->fx_where + fixP->fx_frag->fr_address;
|
|
}
|
|
|
|
/* Indicate whether a fixup against a locally defined
|
|
symbol should be adjusted to be against the section
|
|
symbol. */
|
|
bool
|
|
visium_fix_adjustable (fixS *fix)
|
|
{
|
|
/* We need the symbol name for the VTABLE entries. */
|
|
return (fix->fx_r_type != BFD_RELOC_VTABLE_INHERIT
|
|
&& fix->fx_r_type != BFD_RELOC_VTABLE_ENTRY);
|
|
}
|
|
|
|
/* Update the parity bit of the 4-byte instruction in BUF. */
|
|
static void
|
|
visium_update_parity_bit (char *buf)
|
|
{
|
|
int p1 = (buf[0] & 0x7f) ^ buf[1] ^ buf[2] ^ buf[3];
|
|
int p2 = 0;
|
|
int i;
|
|
|
|
for (i = 1; i <= 8; i++)
|
|
{
|
|
p2 ^= (p1 & 1);
|
|
p1 >>= 1;
|
|
}
|
|
|
|
buf[0] = (buf[0] & 0x7f) | ((p2 << 7) & 0x80);
|
|
}
|
|
|
|
/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
|
|
of an rs_align_code fragment. */
|
|
void
|
|
visium_handle_align (fragS *fragP)
|
|
{
|
|
valueT count
|
|
= fragP->fr_next->fr_address - (fragP->fr_address + fragP->fr_fix);
|
|
valueT fix = count & 3;
|
|
char *p = fragP->fr_literal + fragP->fr_fix;
|
|
|
|
if (fix)
|
|
{
|
|
memset (p, 0, fix);
|
|
p += fix;
|
|
count -= fix;
|
|
fragP->fr_fix += fix;
|
|
}
|
|
|
|
if (count == 0)
|
|
return;
|
|
|
|
fragP->fr_var = 4;
|
|
|
|
if (count > 4 * nop_limit && count <= 131068)
|
|
{
|
|
struct frag *rest;
|
|
|
|
/* Make a branch, then follow with nops. Insert another
|
|
frag to handle the nops. */
|
|
md_number_to_chars (p, 0x78000000 + (count >> 2), 4);
|
|
visium_update_parity_bit (p);
|
|
|
|
rest = xmalloc (SIZEOF_STRUCT_FRAG + 4);
|
|
memcpy (rest, fragP, SIZEOF_STRUCT_FRAG);
|
|
fragP->fr_next = rest;
|
|
rest->fr_address += rest->fr_fix + 4;
|
|
rest->fr_fix = 0;
|
|
/* If we leave the next frag as rs_align_code we'll come here
|
|
again, resulting in a bunch of branches rather than a
|
|
branch followed by nops. */
|
|
rest->fr_type = rs_align;
|
|
p = rest->fr_literal;
|
|
}
|
|
|
|
memset (p, 0, 4);
|
|
}
|
|
|
|
/* Apply a fixS to the frags, now that we know the value it ought to
|
|
hold. */
|
|
void
|
|
md_apply_fix (fixS * fixP, valueT * value, segT segment)
|
|
{
|
|
char *buf = fixP->fx_where + fixP->fx_frag->fr_literal;
|
|
offsetT val;
|
|
long insn;
|
|
|
|
val = *value;
|
|
|
|
gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED);
|
|
|
|
/* Remember value for tc_gen_reloc. */
|
|
fixP->fx_addnumber = val;
|
|
|
|
/* Since DIFF_EXPR_OK is defined, .-foo gets turned into PC
|
|
relative relocs. If this has happened, a non-PC relative
|
|
reloc must be reinstalled with its PC relative version here. */
|
|
if (fixP->fx_pcrel)
|
|
{
|
|
switch (fixP->fx_r_type)
|
|
{
|
|
case BFD_RELOC_8:
|
|
fixP->fx_r_type = BFD_RELOC_8_PCREL;
|
|
break;
|
|
case BFD_RELOC_16:
|
|
fixP->fx_r_type = BFD_RELOC_16_PCREL;
|
|
break;
|
|
case BFD_RELOC_32:
|
|
fixP->fx_r_type = BFD_RELOC_32_PCREL;
|
|
break;
|
|
case BFD_RELOC_VISIUM_HI16:
|
|
fixP->fx_r_type = BFD_RELOC_VISIUM_HI16_PCREL;
|
|
break;
|
|
case BFD_RELOC_VISIUM_LO16:
|
|
fixP->fx_r_type = BFD_RELOC_VISIUM_LO16_PCREL;
|
|
break;
|
|
case BFD_RELOC_VISIUM_IM16:
|
|
fixP->fx_r_type = BFD_RELOC_VISIUM_IM16_PCREL;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* If this is a data relocation, just output VAL. */
|
|
switch (fixP->fx_r_type)
|
|
{
|
|
case BFD_RELOC_8:
|
|
case BFD_RELOC_8_PCREL:
|
|
md_number_to_chars (buf, val, 1);
|
|
break;
|
|
case BFD_RELOC_16:
|
|
case BFD_RELOC_16_PCREL:
|
|
md_number_to_chars (buf, val, 2);
|
|
break;
|
|
case BFD_RELOC_32:
|
|
case BFD_RELOC_32_PCREL:
|
|
md_number_to_chars (buf, val, 4);
|
|
break;
|
|
case BFD_RELOC_VTABLE_INHERIT:
|
|
case BFD_RELOC_VTABLE_ENTRY:
|
|
fixP->fx_done = 0;
|
|
break;
|
|
default:
|
|
/* It's a relocation against an instruction. */
|
|
insn = bfd_getb32 ((unsigned char *) buf);
|
|
|
|
switch (fixP->fx_r_type)
|
|
{
|
|
case BFD_RELOC_VISIUM_REL16:
|
|
if (fixP->fx_addsy == NULL
|
|
|| (S_IS_DEFINED (fixP->fx_addsy)
|
|
&& S_GET_SEGMENT (fixP->fx_addsy) == segment))
|
|
{
|
|
if (val > 0x1fffc || val < -0x20000)
|
|
as_bad_where
|
|
(fixP->fx_file, fixP->fx_line,
|
|
"16-bit word displacement out of range: value = %d",
|
|
(int) val);
|
|
val = (val >> 2);
|
|
|
|
insn = (insn & 0xffff0000) | (val & 0x0000ffff);
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_VISIUM_HI16:
|
|
case BFD_RELOC_VISIUM_HI16_PCREL:
|
|
if (fixP->fx_addsy == NULL)
|
|
insn = (insn & 0xffff0000) | ((val >> 16) & 0x0000ffff);
|
|
break;
|
|
|
|
case BFD_RELOC_VISIUM_LO16:
|
|
case BFD_RELOC_VISIUM_LO16_PCREL:
|
|
if (fixP->fx_addsy == NULL)
|
|
insn = (insn & 0xffff0000) | (val & 0x0000ffff);
|
|
break;
|
|
|
|
case BFD_RELOC_VISIUM_IM16:
|
|
case BFD_RELOC_VISIUM_IM16_PCREL:
|
|
if (fixP->fx_addsy == NULL)
|
|
{
|
|
if ((val & 0xffff0000) != 0)
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
"16-bit immediate out of range: value = %d",
|
|
(int) val);
|
|
|
|
insn = (insn & 0xffff0000) | val;
|
|
}
|
|
break;
|
|
|
|
case BFD_RELOC_NONE:
|
|
default:
|
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
|
"bad or unhandled relocation type: 0x%02x",
|
|
fixP->fx_r_type);
|
|
break;
|
|
}
|
|
|
|
bfd_putb32 (insn, (unsigned char *) buf);
|
|
visium_update_parity_bit (buf);
|
|
break;
|
|
}
|
|
|
|
/* Are we finished with this relocation now? */
|
|
if (fixP->fx_addsy == NULL)
|
|
fixP->fx_done = 1;
|
|
}
|
|
|
|
char *
|
|
parse_exp (char *s, expressionS * op)
|
|
{
|
|
char *save = input_line_pointer;
|
|
char *new;
|
|
|
|
if (!s)
|
|
{
|
|
return s;
|
|
}
|
|
|
|
input_line_pointer = s;
|
|
expression (op);
|
|
new = input_line_pointer;
|
|
input_line_pointer = save;
|
|
return new;
|
|
}
|
|
|
|
/* If the given string is a Visium opcode mnemonic return the code
|
|
otherwise return -1. Use binary chop to find matching entry. */
|
|
static int
|
|
get_opcode (int *code, enum addressing_mode *mode, char *flags, char *mnem)
|
|
{
|
|
int l = 0;
|
|
int r = sizeof (opcode_table) / sizeof (struct opcode_entry) - 1;
|
|
|
|
do
|
|
{
|
|
int mid = (l + r) / 2;
|
|
int ans = strcmp (mnem, opcode_table[mid].mnem);
|
|
|
|
if (ans < 0)
|
|
r = mid - 1;
|
|
else if (ans > 0)
|
|
l = mid + 1;
|
|
else
|
|
{
|
|
*code = opcode_table[mid].code;
|
|
*mode = opcode_table[mid].mode;
|
|
*flags = opcode_table[mid].flags;
|
|
|
|
return 0;
|
|
}
|
|
}
|
|
while (l <= r);
|
|
|
|
return -1;
|
|
}
|
|
|
|
/* This function is called when the assembler starts up. It is called
|
|
after the options have been parsed and the output file has been
|
|
opened. */
|
|
void
|
|
md_begin (void)
|
|
{
|
|
switch (visium_arch)
|
|
{
|
|
case VISIUM_ARCH_DEF:
|
|
break;
|
|
case VISIUM_ARCH_MCM24:
|
|
visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5;
|
|
visium_flags |= EF_VISIUM_ARCH_MCM24;
|
|
break;
|
|
case VISIUM_ARCH_MCM:
|
|
visium_opcode_arch = VISIUM_OPCODE_ARCH_GR5;
|
|
visium_flags |= EF_VISIUM_ARCH_MCM;
|
|
break;
|
|
case VISIUM_ARCH_GR6:
|
|
visium_opcode_arch = VISIUM_OPCODE_ARCH_GR6;
|
|
visium_flags |= EF_VISIUM_ARCH_MCM | EF_VISIUM_ARCH_GR6;
|
|
nop_limit = 2;
|
|
break;
|
|
default:
|
|
gas_assert (0);
|
|
}
|
|
|
|
bfd_set_private_flags (stdoutput, visium_flags);
|
|
}
|
|
|
|
/* This is identical to the md_atof in m68k.c. I think this is right,
|
|
but I'm not sure.
|
|
|
|
Turn a string in input_line_pointer into a floating point constant of type
|
|
type, and store the appropriate bytes in *litP. The number of LITTLENUMS
|
|
emitted is stored in *sizeP . An error message is returned,
|
|
or NULL on OK. */
|
|
|
|
const char *
|
|
md_atof (int type, char *litP, int *sizeP)
|
|
{
|
|
int i, prec;
|
|
LITTLENUM_TYPE words[MAX_LITTLENUMS];
|
|
char *t;
|
|
|
|
switch (type)
|
|
{
|
|
case 'f':
|
|
case 'F':
|
|
case 's':
|
|
case 'S':
|
|
prec = 2;
|
|
break;
|
|
|
|
case 'd':
|
|
case 'D':
|
|
case 'r':
|
|
case 'R':
|
|
prec = 4;
|
|
break;
|
|
|
|
case 'x':
|
|
case 'X':
|
|
prec = 6;
|
|
break;
|
|
|
|
case 'p':
|
|
case 'P':
|
|
prec = 6;
|
|
break;
|
|
|
|
default:
|
|
*sizeP = 0;
|
|
return _("Bad call to MD_ATOF()");
|
|
}
|
|
|
|
t = atof_ieee (input_line_pointer, type, words);
|
|
if (t)
|
|
input_line_pointer = t;
|
|
*sizeP = prec * sizeof (LITTLENUM_TYPE);
|
|
|
|
if (target_big_endian)
|
|
{
|
|
for (i = 0; i < prec; i++)
|
|
{
|
|
md_number_to_chars (litP, (valueT) words[i],
|
|
sizeof (LITTLENUM_TYPE));
|
|
litP += sizeof (LITTLENUM_TYPE);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
for (i = prec - 1; i >= 0; i--)
|
|
{
|
|
md_number_to_chars (litP, (valueT) words[i],
|
|
sizeof (LITTLENUM_TYPE));
|
|
litP += sizeof (LITTLENUM_TYPE);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static inline char *
|
|
skip_space (char *s)
|
|
{
|
|
while (*s == ' ' || *s == '\t')
|
|
++s;
|
|
|
|
return s;
|
|
}
|
|
|
|
static int
|
|
parse_gen_reg (char **sptr, int *rptr)
|
|
{
|
|
char *s = skip_space (*sptr);
|
|
char buf[10];
|
|
int cnt;
|
|
int l, r;
|
|
|
|
cnt = 0;
|
|
memset (buf, '\0', 10);
|
|
while ((ISALNUM (*s)) && cnt < 10)
|
|
buf[cnt++] = TOLOWER (*s++);
|
|
|
|
l = 0;
|
|
r = sizeof (gen_reg_table) / sizeof (struct reg_entry) - 1;
|
|
|
|
do
|
|
{
|
|
int mid = (l + r) / 2;
|
|
int ans = strcmp (buf, gen_reg_table[mid].name);
|
|
|
|
if (ans < 0)
|
|
r = mid - 1;
|
|
else if (ans > 0)
|
|
l = mid + 1;
|
|
else
|
|
{
|
|
*rptr = gen_reg_table[mid].code;
|
|
*sptr = s;
|
|
return 0;
|
|
}
|
|
}
|
|
while (l <= r);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
parse_fp_reg (char **sptr, int *rptr)
|
|
{
|
|
char *s = skip_space (*sptr);
|
|
char buf[10];
|
|
int cnt;
|
|
int l, r;
|
|
|
|
cnt = 0;
|
|
memset (buf, '\0', 10);
|
|
while ((ISALNUM (*s)) && cnt < 10)
|
|
buf[cnt++] = TOLOWER (*s++);
|
|
|
|
l = 0;
|
|
r = sizeof (fp_reg_table) / sizeof (struct reg_entry) - 1;
|
|
|
|
do
|
|
{
|
|
int mid = (l + r) / 2;
|
|
int ans = strcmp (buf, fp_reg_table[mid].name);
|
|
|
|
if (ans < 0)
|
|
r = mid - 1;
|
|
else if (ans > 0)
|
|
l = mid + 1;
|
|
else
|
|
{
|
|
*rptr = fp_reg_table[mid].code;
|
|
*sptr = s;
|
|
return 0;
|
|
}
|
|
}
|
|
while (l <= r);
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
parse_cc (char **sptr, int *rptr)
|
|
{
|
|
char *s = skip_space (*sptr);
|
|
char buf[10];
|
|
int cnt;
|
|
int l, r;
|
|
|
|
cnt = 0;
|
|
memset (buf, '\0', 10);
|
|
while ((ISALNUM (*s)) && cnt < 10)
|
|
buf[cnt++] = TOLOWER (*s++);
|
|
|
|
l = 0;
|
|
r = sizeof (cc_table) / sizeof (struct cc_entry) - 1;
|
|
|
|
do
|
|
{
|
|
int mid = (l + r) / 2;
|
|
int ans = strcmp (buf, cc_table[mid].name);
|
|
|
|
if (ans < 0)
|
|
r = mid - 1;
|
|
else if (ans > 0)
|
|
l = mid + 1;
|
|
else
|
|
{
|
|
*rptr = cc_table[mid].code;
|
|
*sptr = s;
|
|
return 0;
|
|
}
|
|
}
|
|
while (l <= r);
|
|
|
|
return -1;
|
|
}
|
|
|
|
/* Previous dest is the destination register number of the instruction
|
|
before the current one. */
|
|
static int previous_dest = 0;
|
|
static int previous_mode = 0;
|
|
static int condition_code = 0;
|
|
static int this_dest = 0;
|
|
static int this_mode = 0;
|
|
|
|
|
|
/* This is the main function in this file. It takes a line of assembly language
|
|
source code and assembles it. Note, labels and pseudo ops have already
|
|
been removed, so too has leading white space. */
|
|
void
|
|
md_assemble (char *str0)
|
|
{
|
|
char *str = str0;
|
|
int cnt;
|
|
char mnem[10];
|
|
int opcode;
|
|
enum addressing_mode amode;
|
|
char arch_flags;
|
|
int ans;
|
|
|
|
char *output;
|
|
int reloc = 0;
|
|
relax_substateT relax = 0;
|
|
expressionS e1;
|
|
int r1, r2, r3;
|
|
int cc;
|
|
int indx;
|
|
|
|
/* Initialize the expression. */
|
|
e1.X_op = O_absent;
|
|
|
|
/* Initialize destination register.
|
|
If the instruction we just looked at is in the delay slot of an
|
|
unconditional branch, then there is no index hazard. */
|
|
if ((previous_mode == mode_cad || previous_mode == mode_ci)
|
|
&& condition_code == 15)
|
|
this_dest = 0;
|
|
|
|
previous_dest = this_dest;
|
|
previous_mode = this_mode;
|
|
this_dest = 0;
|
|
|
|
/* Drop leading whitespace (probably not required). */
|
|
while (*str == ' ')
|
|
str++;
|
|
|
|
/* Get opcode mnemonic and make sure it's in lower case. */
|
|
cnt = 0;
|
|
memset (mnem, '\0', 10);
|
|
while ((ISALNUM (*str) || *str == '.' || *str == '_') && cnt < 10)
|
|
mnem[cnt++] = TOLOWER (*str++);
|
|
|
|
/* Look up mnemonic in opcode table, and get the code,
|
|
the instruction format, and the flags that indicate
|
|
which family members support this mnemonic. */
|
|
if (get_opcode (&opcode, &amode, &arch_flags, mnem) < 0)
|
|
{
|
|
as_bad ("Unknown instruction mnemonic `%s'", mnem);
|
|
return;
|
|
}
|
|
|
|
if ((VISIUM_OPCODE_ARCH_MASK (visium_opcode_arch) & arch_flags) == 0)
|
|
{
|
|
as_bad ("Architecture mismatch on `%s'", mnem);
|
|
return;
|
|
}
|
|
|
|
this_mode = amode;
|
|
|
|
switch (amode)
|
|
{
|
|
case mode_d:
|
|
/* register :=
|
|
Example:
|
|
readmda r1 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 10);
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_a:
|
|
/* op= register
|
|
Example: asld r1 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 16);
|
|
break;
|
|
|
|
case mode_ab:
|
|
/* register * register
|
|
Example:
|
|
mults r1,r2 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 16) | (r2 << 4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_da:
|
|
/* register := register
|
|
Example:
|
|
extb.l r1,r2 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_dab:
|
|
/* register := register * register
|
|
Example:
|
|
add.l r1,r2,r3 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got three regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_iab:
|
|
/* 5-bit immediate * register * register
|
|
Example:
|
|
eamwrite 3,r1,r2 */
|
|
str = parse_exp (str, &e1);
|
|
str = skip_space (str);
|
|
if (e1.X_op != O_absent && *str == ',')
|
|
{
|
|
int eam_op = e1.X_add_number;
|
|
|
|
str = skip_space (str + 1);
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got three operands, assemble instruction. */
|
|
if (eam_op < 0 || eam_op > 31)
|
|
{
|
|
as_bad ("eam_op out of range");
|
|
}
|
|
opcode |= ((eam_op & 0x1f) << 10) | (r2 << 16) | (r3 << 4);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("EAM_OP required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_0ab:
|
|
/* zero * register * register
|
|
Example:
|
|
cmp.l r1,r2 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 16) | (r2 << 4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_da0:
|
|
/* register * register * zero
|
|
Example:
|
|
move.l r1,r2 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_cad:
|
|
/* condition * register * register
|
|
Example:
|
|
bra tr,r1,r2 */
|
|
ans = parse_cc (&str, &cc);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("condition code required");
|
|
return;
|
|
}
|
|
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str = skip_space (str + 1);
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
|
|
/* Got three operands, assemble instruction. */
|
|
opcode |= (cc << 27) | (r2 << 16) | (r3 << 10);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
|
|
if (previous_mode == mode_cad || previous_mode == mode_ci)
|
|
as_bad ("branch instruction in delay slot");
|
|
|
|
/* For the GR6, BRA insns must be aligned on 64-bit boundaries. */
|
|
if (visium_arch == VISIUM_ARCH_GR6)
|
|
do_align (3, NULL, 0, 0);
|
|
|
|
this_dest = r3;
|
|
condition_code = cc;
|
|
break;
|
|
|
|
case mode_das:
|
|
/* register := register * 5-bit immediate/register shift count
|
|
Example:
|
|
asl.l r1,r2,4 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r3);
|
|
if (ans == 0)
|
|
{
|
|
opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
|
|
}
|
|
else
|
|
{
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
int imm = e1.X_add_number;
|
|
|
|
if (imm < 0 || imm > 31)
|
|
as_bad ("immediate value out of range");
|
|
|
|
opcode |=
|
|
(r1 << 10) | (r2 << 16) | (1 << 9) | ((imm & 0x1f) <<
|
|
4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate operand required");
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_di:
|
|
/* register := 5-bit immediate
|
|
Example:
|
|
eamread r1,3 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
int opnd2 = e1.X_add_number;
|
|
|
|
if (opnd2 < 0 || opnd2 > 31)
|
|
{
|
|
as_bad ("immediate operand out of range");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 10) | ((opnd2 & 0x1f) << 4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate operand required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate operand required");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_ir:
|
|
/* 5-bit immediate * register, e.g. trace 1,r1 */
|
|
str = parse_exp (str, &e1);
|
|
str = skip_space (str);
|
|
if (e1.X_op == O_constant && *str == ',')
|
|
{
|
|
int opnd1 = e1.X_add_number;
|
|
|
|
str = skip_space (str + 1);
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
|
|
/* Got two operands, assemble instruction. */
|
|
if (opnd1 < 0 || opnd1 > 31)
|
|
{
|
|
as_bad ("1st operand out of range");
|
|
}
|
|
opcode |= ((opnd1 & 0x1f) << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("Immediate operand required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_ai:
|
|
/* register *= 16-bit unsigned immediate
|
|
Example:
|
|
addi r1,123 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
opcode |= (r1 << 16);
|
|
|
|
str = skip_space (str);
|
|
if (*str != ',')
|
|
{
|
|
as_bad ("immediate value missing");
|
|
return;
|
|
}
|
|
this_dest = r1;
|
|
/* Fall through. */
|
|
|
|
case mode_i:
|
|
/* MOVIL/WRTL traditionally get an implicit "%l" applied
|
|
to their immediate value. For other opcodes, unless
|
|
the immediate value is decorated with "%u" or "%l"
|
|
it must be in the range 0 .. 65535. */
|
|
if ((opcode & 0x7fe00000) == 0x04800000
|
|
|| (opcode & 0x7fe00000) == 0x05000000)
|
|
reloc = BFD_RELOC_VISIUM_LO16;
|
|
else
|
|
reloc = BFD_RELOC_VISIUM_IM16;
|
|
|
|
str = skip_space (str + 1);
|
|
|
|
if (*str == '%')
|
|
{
|
|
if (str[1] == 'u')
|
|
reloc = BFD_RELOC_VISIUM_HI16;
|
|
else if (str[1] == 'l')
|
|
reloc = BFD_RELOC_VISIUM_LO16;
|
|
else
|
|
{
|
|
as_bad ("bad char after %%");
|
|
return;
|
|
}
|
|
|
|
str += 2;
|
|
}
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op != O_absent)
|
|
{
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
int imm = e1.X_add_number;
|
|
|
|
if (reloc == BFD_RELOC_VISIUM_HI16)
|
|
opcode |= ((imm >> 16) & 0xffff);
|
|
else if (reloc == BFD_RELOC_VISIUM_LO16)
|
|
opcode |= (imm & 0xffff);
|
|
else
|
|
{
|
|
if (imm < 0 || imm > 0xffff)
|
|
as_bad ("immediate value out of range");
|
|
|
|
opcode |= (imm & 0xffff);
|
|
}
|
|
/* No relocation is needed. */
|
|
reloc = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate value missing");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_bax:
|
|
/* register * register * 5-bit immediate,
|
|
SourceB * SourceA * Index
|
|
Examples
|
|
write.l (r1),r2
|
|
write.l 3(r1),r2 */
|
|
str = skip_space (str);
|
|
|
|
indx = 0;
|
|
if (*str != '(')
|
|
{
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
indx = e1.X_add_number;
|
|
|
|
if (indx < 0 || indx > 31)
|
|
{
|
|
as_bad ("Index out of range");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("Index(SourceA) required");
|
|
return;
|
|
}
|
|
}
|
|
|
|
str = skip_space (str);
|
|
|
|
if (*str != '(')
|
|
{
|
|
as_bad ("Index(SourceA) required");
|
|
return;
|
|
}
|
|
|
|
str = skip_space (str + 1);
|
|
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str != ')')
|
|
{
|
|
as_bad ("(SourceA) required");
|
|
return;
|
|
}
|
|
str = skip_space (str + 1);
|
|
|
|
if (*str == ',')
|
|
{
|
|
str = skip_space (str + 1);
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceB register required");
|
|
return;
|
|
}
|
|
|
|
opcode |= (r1 << 16) | (r2 << 4) | ((indx & 0x1f) << 10);
|
|
|
|
if (indx != 0 && previous_mode == mode_cad)
|
|
{
|
|
/* We're in a delay slot.
|
|
If the base reg is the destination of the branch, then issue
|
|
an error message.
|
|
Otherwise it is safe to use the base and index. */
|
|
if (previous_dest != 0 && r1 == previous_dest)
|
|
{
|
|
as_bad ("base register not ready");
|
|
return;
|
|
}
|
|
}
|
|
else if (previous_dest != 0
|
|
&& r1 == previous_dest
|
|
&& (visium_arch == VISIUM_ARCH_MCM
|
|
|| visium_arch == VISIUM_ARCH_MCM24
|
|
|| (visium_arch == VISIUM_ARCH_DEF && indx != 0)))
|
|
{
|
|
as_warn ("base register not ready, NOP inserted.");
|
|
/* Insert a NOP before the write instruction. */
|
|
output = frag_more (4);
|
|
memset (output, 0, 4);
|
|
}
|
|
break;
|
|
|
|
case mode_dax:
|
|
/* register := register * 5-bit immediate
|
|
Examples:
|
|
read.b r1,(r2)
|
|
read.w r1,3(r2) */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str != ',')
|
|
{
|
|
as_bad ("SourceA required");
|
|
return;
|
|
}
|
|
str = skip_space (str + 1);
|
|
|
|
indx = 0;
|
|
if (*str != '(')
|
|
{
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
indx = e1.X_add_number;
|
|
|
|
if (indx < 0 || indx > 31)
|
|
{
|
|
as_bad ("Index out of range");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("Immediate 0 to 31 required");
|
|
return;
|
|
}
|
|
}
|
|
if (*str != '(')
|
|
{
|
|
as_bad ("(SourceA) required");
|
|
return;
|
|
}
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str != ')')
|
|
{
|
|
as_bad ("(SourceA) required");
|
|
return;
|
|
}
|
|
str++;
|
|
opcode |= (r1 << 10) | (r2 << 16) | ((indx & 0x1f) << 4);
|
|
this_dest = r1;
|
|
|
|
if (indx != 0 && previous_mode == mode_cad)
|
|
{
|
|
/* We're in a delay slot.
|
|
If the base reg is the destination of the branch, then issue
|
|
an error message.
|
|
Otherwise it is safe to use the base and index. */
|
|
if (previous_dest != 0 && r2 == previous_dest)
|
|
{
|
|
as_bad ("base register not ready");
|
|
return;
|
|
}
|
|
}
|
|
else if (previous_dest != 0
|
|
&& r2 == previous_dest
|
|
&& (visium_arch == VISIUM_ARCH_MCM
|
|
|| visium_arch == VISIUM_ARCH_MCM24
|
|
|| (visium_arch == VISIUM_ARCH_DEF && indx != 0)))
|
|
{
|
|
as_warn ("base register not ready, NOP inserted.");
|
|
/* Insert a NOP before the read instruction. */
|
|
output = frag_more (4);
|
|
memset (output, 0, 4);
|
|
}
|
|
break;
|
|
|
|
case mode_s:
|
|
/* special mode
|
|
Example:
|
|
nop */
|
|
str = skip_space (str);
|
|
break;
|
|
|
|
case mode_ci:
|
|
/* condition * 16-bit signed word displacement
|
|
Example:
|
|
brr L1 */
|
|
ans = parse_cc (&str, &cc);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("condition code required");
|
|
return;
|
|
}
|
|
opcode |= (cc << 27);
|
|
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str = skip_space (str + 1);
|
|
str = parse_exp (str, &e1);
|
|
if (e1.X_op != O_absent)
|
|
{
|
|
if (e1.X_op == O_constant)
|
|
{
|
|
int imm = e1.X_add_number;
|
|
|
|
if (imm < -32768 || imm > 32767)
|
|
as_bad ("immediate value out of range");
|
|
|
|
/* The GR6 doesn't correctly handle a 0 displacement
|
|
so we insert a NOP and change it to -1. */
|
|
if (imm == 0 && cc != 0 && visium_arch == VISIUM_ARCH_GR6)
|
|
{
|
|
output = frag_more (4);
|
|
memset (output, 0, 4);
|
|
imm = -1;
|
|
}
|
|
|
|
opcode |= (imm & 0xffff);
|
|
}
|
|
else if (e1.X_op == O_symbol)
|
|
{
|
|
/* The GR6 doesn't correctly handle a 0 displacement
|
|
so the instruction requires relaxation. */
|
|
if (cc != 0 && visium_arch == VISIUM_ARCH_GR6)
|
|
relax = amode;
|
|
else
|
|
reloc = BFD_RELOC_VISIUM_REL16;
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate value missing");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate value missing");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("immediate value missing");
|
|
return;
|
|
}
|
|
|
|
if (previous_mode == mode_cad || previous_mode == mode_ci)
|
|
as_bad ("branch instruction in delay slot");
|
|
|
|
condition_code = cc;
|
|
break;
|
|
|
|
case mode_fdab:
|
|
/* float := float * float
|
|
Example
|
|
fadd f4,f3,f2 */
|
|
ans = parse_fp_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point destination register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got 3 floating regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_ifdab:
|
|
/* 4-bit immediate * float * float * float
|
|
Example
|
|
fpinst 10,f1,f2,f3 */
|
|
str = parse_exp (str, &e1);
|
|
str = skip_space (str);
|
|
if (e1.X_op != O_absent && *str == ',')
|
|
{
|
|
int finst = e1.X_add_number;
|
|
|
|
str = skip_space (str + 1);
|
|
ans = parse_fp_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point destination register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got immediate and 3 floating regs,
|
|
assemble instruction. */
|
|
if (finst < 0 || finst > 15)
|
|
as_bad ("finst out of range");
|
|
|
|
opcode |=
|
|
((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 <<
|
|
4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("finst missing");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_idfab:
|
|
/* 4-bit immediate * register * float * float
|
|
Example
|
|
fpuread 4,r25,f2,f3 */
|
|
str = parse_exp (str, &e1);
|
|
str = skip_space (str);
|
|
if (e1.X_op != O_absent && *str == ',')
|
|
{
|
|
int finst = e1.X_add_number;
|
|
|
|
str = skip_space (str + 1);
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("destination general register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got immediate and 3 floating regs,
|
|
assemble instruction. */
|
|
if (finst < 0 || finst > 15)
|
|
as_bad ("finst out of range");
|
|
|
|
opcode |=
|
|
((finst & 0xf) << 27) | (r1 << 10) | (r2 << 16) | (r3 <<
|
|
4);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("finst missing");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_fda:
|
|
/* float := float
|
|
Example
|
|
fsqrt f4,f3 */
|
|
ans = parse_fp_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point destination register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point source register required");
|
|
return;
|
|
}
|
|
|
|
/* Got 2 floating regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point source register required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_fdra:
|
|
/* float := register
|
|
Example
|
|
fload f15,r6 */
|
|
ans = parse_fp_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point destination register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("SourceA general register required");
|
|
return;
|
|
}
|
|
|
|
/* Got 2 regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("SourceA general register required");
|
|
return;
|
|
}
|
|
break;
|
|
|
|
case mode_rdfab:
|
|
/* register := float * float
|
|
Example
|
|
fcmp r0,f4,f8
|
|
For the GR6, register must be r0 and can be omitted. */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
if (visium_opcode_arch == VISIUM_OPCODE_ARCH_GR5)
|
|
{
|
|
as_bad ("Dest general register required");
|
|
return;
|
|
}
|
|
r1 = 0;
|
|
}
|
|
else
|
|
{
|
|
if (r1 != 0 && visium_opcode_arch != VISIUM_OPCODE_ARCH_GR5)
|
|
{
|
|
as_bad ("FCMP/FCMPE can only use r0 as Dest register");
|
|
return;
|
|
}
|
|
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
str++;
|
|
else
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
}
|
|
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceA register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point SourceB register required");
|
|
return;
|
|
}
|
|
|
|
/* Got 3 regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16) | (r3 << 4);
|
|
}
|
|
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_rdfa:
|
|
/* register := float
|
|
Example
|
|
fstore r5,f12 */
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("Dest general register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_fp_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("floating point source register required");
|
|
return;
|
|
}
|
|
|
|
/* Got 2 regs, assemble instruction. */
|
|
opcode |= (r1 << 10) | (r2 << 16);
|
|
}
|
|
else
|
|
{
|
|
as_bad ("floating point source register required");
|
|
return;
|
|
}
|
|
|
|
this_dest = r1;
|
|
break;
|
|
|
|
case mode_rrr:
|
|
/* register register register, all sources and destinations
|
|
Example:
|
|
bmd r1,r2,r3 */
|
|
|
|
ans = parse_gen_reg (&str, &r1);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("destination address register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r2);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("source address register required");
|
|
return;
|
|
}
|
|
str = skip_space (str);
|
|
if (*str == ',')
|
|
{
|
|
str++;
|
|
ans = parse_gen_reg (&str, &r3);
|
|
if (ans < 0)
|
|
{
|
|
as_bad ("count register required");
|
|
return;
|
|
}
|
|
|
|
/* We insist on three registers but the opcode can only use
|
|
r1,r2,r3. */
|
|
if (r1 != 1 || r2 != 2 || r3 != 3)
|
|
{
|
|
as_bad ("BMI/BMD can only use format op r1,r2,r3");
|
|
return;
|
|
}
|
|
|
|
/* Opcode is unmodified by what comes out of the table. */
|
|
}
|
|
else
|
|
{
|
|
as_bad ("register required");
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
as_bad ("register required");
|
|
return;
|
|
}
|
|
|
|
this_dest = r1;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (relax)
|
|
output = frag_var (rs_machine_dependent, 8, 4, relax, e1.X_add_symbol,
|
|
e1.X_add_number, NULL);
|
|
else
|
|
output = frag_more (4);
|
|
|
|
/* Build the 32-bit instruction in a host-endian-neutral fashion. */
|
|
output[0] = (opcode >> 24) & 0xff;
|
|
output[1] = (opcode >> 16) & 0xff;
|
|
output[2] = (opcode >> 8) & 0xff;
|
|
output[3] = (opcode >> 0) & 0xff;
|
|
|
|
if (relax)
|
|
/* The size of the instruction is unknown, so tie the debug info to the
|
|
start of the instruction. */
|
|
dwarf2_emit_insn (0);
|
|
else
|
|
{
|
|
if (reloc)
|
|
fix_new_exp (frag_now, output - frag_now->fr_literal, 4, &e1,
|
|
reloc == BFD_RELOC_VISIUM_REL16, reloc);
|
|
else
|
|
visium_update_parity_bit (output);
|
|
|
|
dwarf2_emit_insn (4);
|
|
}
|
|
|
|
if (*str != '\0')
|
|
as_bad ("junk after instruction");
|
|
}
|
|
|
|
void
|
|
visium_cfi_frame_initial_instructions (void)
|
|
{
|
|
/* The CFA is in SP on function entry. */
|
|
cfi_add_CFA_def_cfa (23, 0);
|
|
}
|
|
|
|
int
|
|
visium_regname_to_dw2regnum (char *regname)
|
|
{
|
|
if (!regname[0])
|
|
return -1;
|
|
|
|
if (regname[0] == 'f' && regname[1] == 'p' && !regname[2])
|
|
return 22;
|
|
|
|
if (regname[0] == 's' && regname[1] == 'p' && !regname[2])
|
|
return 23;
|
|
|
|
if (regname[0] == 'm' && regname[1] == 'd' && !regname[3])
|
|
switch (regname[2])
|
|
{
|
|
case 'b': return 32;
|
|
case 'a': return 33;
|
|
case 'c': return 34;
|
|
default : return -1;
|
|
}
|
|
|
|
if (regname[0] == 'f' || regname[0] == 'r')
|
|
{
|
|
char *p;
|
|
unsigned int regnum = strtoul (regname + 1, &p, 10);
|
|
if (*p)
|
|
return -1;
|
|
if (regnum >= (regname[0] == 'f' ? 16 : 32))
|
|
return -1;
|
|
if (regname[0] == 'f')
|
|
regnum += 35;
|
|
return regnum;
|
|
}
|
|
|
|
return -1;
|
|
}
|