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https://sourceware.org/git/binutils-gdb.git
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b763d508db
Commit 6ff00b5e12 ("x86/Intel: correct permitted operand sizes for
AVX512 scatter/gather") brought the assembler side of AVX512 S/G insn
handling in line with AVX2's, but the disassembler side was forgotten.
This has the benefit of
- allowing to fold a number of table entries,
- rendering a few #define-s and enumerators unused.
52 lines
1.5 KiB
C
52 lines
1.5 KiB
C
/* REG_EVEX_0F71 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vpsrlw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "vpsraw", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ "vpsllw", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F72 */
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{
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{ "vpror%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ "vprol%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ VEX_W_TABLE (EVEX_W_0F72_R_2) },
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{ Bad_Opcode },
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{ "vpsra%DQ", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F72_R_6) },
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},
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/* REG_EVEX_0F73 */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_2) },
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{ "vpsrldq", { Vex, EXx, Ib }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (EVEX_W_0F73_R_6) },
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{ "vpslldq", { Vex, EXx, Ib }, PREFIX_DATA },
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},
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/* REG_EVEX_0F38C6_M_0_L_2 */
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{
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{ Bad_Opcode },
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{ "vgatherpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ "vgatherpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vscatterpf0dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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{ "vscatterpf1dp%XW", { MVexVSIBDWpX }, PREFIX_DATA },
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},
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/* REG_EVEX_0F38C7_M_0_L_2_W_0 */
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{
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{ Bad_Opcode },
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{ "vgatherpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ "vgatherpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "vscatterpf0qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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{ "vscatterpf1qp%XW", { MVexVSIBQWpX }, PREFIX_DATA },
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},
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