Jeff Law 477904ca75 Fix for v850e divq instruction ... This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch.		2022-04-06 11:10:40 -04:00
..
aarch64	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
arm	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
avr	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
bfin	sim: bfin: migrate to standard uintXX_t types	2022-01-06 01:17:38 -05:00
bpf	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
common	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
cr16	sim: cr16: migrate to standard uintXX_t types	2022-01-06 01:17:37 -05:00
cris	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
d10v	sim: d10v: migrate to standard uintXX_t types	2022-01-06 01:17:37 -05:00
erc32	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
example-synacor	sim: synacor: migrate to standard uintXX_t types	2022-01-06 01:17:38 -05:00
frv	sim: tweak copyright lines for gnulib update-copyright	2022-01-01 13:14:01 -05:00
ft32	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
h8300	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
igen	sim: igen: migrate to standard uintXX_t types	2022-01-06 01:17:38 -05:00
iq2000	sim: iq2000: migrate to standard uintXX_t types	2022-01-06 01:17:38 -05:00
lm32	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
m4	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
m32c	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
m32r	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
m68hc11	sim: m68hc11: migrate to standard uintXX_t types	2022-01-06 01:17:37 -05:00
mcore	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
microblaze	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
mips	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
mn10300	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
moxie	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
msp430	sim: msp430: migrate to standard uintXX_t types	2022-01-06 01:17:38 -05:00
or1k	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
ppc	sim: fix “alligned” typos	2022-03-24 10:34:51 -04:00
pru	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
riscv	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
rl78	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
rx	sim: fixes for libopcodes styled disassembler	2022-04-04 22:41:24 +01:00
sh	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
testsuite	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
v850	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
.gitignore	sim: drop unused gentmap & nltvals.def logic	2021-11-28 13:24:00 -05:00
aclocal.m4	sim: unify reserved instruction bits settings	2021-07-01 20:53:00 -04:00
arch-subdir.mk.in	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
config.h.in	sim: bfin: add support for SDL2	2021-09-13 22:45:19 -04:00
configure	sim: add arch/.gdbinit stub scripts	2022-03-28 23:10:34 -04:00
configure.ac	sim: add arch/.gdbinit stub scripts	2022-03-28 23:10:34 -04:00
COPYING	sim: clarify license text via COPYING file	2021-11-06 01:44:06 -04:00
gdbinit.in	sim: gdbinit: hoist setup to common code	2022-02-21 13:57:33 -05:00
MAINTAINERS	gdb/sim: update my email address	2021-11-02 09:20:24 +00:00
Makefile.am	Automatic Copyright Year update after running gdb/copyright.py	2022-01-01 19:13:23 +04:00
Makefile.in	sim: add arch/.gdbinit stub scripts	2022-03-28 23:10:34 -04:00
README-HACKING	sim: nltvals: pull target syscalls out into a dedicated source file	2021-11-28 13:23:57 -05:00