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ebcfd86a2e
masking facility for PATH3 transfers.
[ChangeLog.sky]
Sun Apr 5 12:11:45 1998 Frank Ch. Eigler <fche@cygnus.com>
* sky-libvpe.c (exec-inst): Added "M" bit detection for upper
instruction.
* sky-pke.c (pke_check_stall): Added more assertions.
(pke_code_mskpath3): Use new GPUIF M3P control register.
* sky-pke.h (VU[01]_CIA): New macros that give VU CIA
pseudo-register addresses.
* sky-vu.h (vu_device, VectorUnitState): Merged structs.
(VectorUnitState.mflag): New field.
(VU_REG_{CMSAR0,CMSAR1,FBRST}) Added missing control registers.
* sky-vu.c (vu0_busy): New function.
(vu0_q_busy): New function.
(vu0_macro_issue): New function.
(vu0_micro_interlock_released): New function.
(vu0_busy_in_{micro,macro}_mode): Deleted stubs.
(vu0_macro_hazard_check): Deleted stubs.
(vu_attach): Adapted code to merged device & state struct.
(read_vu_special_reg): Compute VBS0/VBS1 bits in STAT register.
[ChangeLog]
start-sanitize-sky
Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
* interp.c (*): Adapt code to merged VU device & state structs.
(decode_coproc): Execute COP2 each macroinstruction without
pipelining, by stepping VU to completion state. Adapted to
read_vu_*_reg style of register access.
* mips.igen ([SL]QC2): Removed these COP2 instructions.
* r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
* sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
end-sanitize-sky
466 lines
14 KiB
C
466 lines
14 KiB
C
/* Copyright (C) 1998, Cygnus Solutions */
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#ifndef H_PKE_H
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#define H_PKE_H
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#include "sim-main.h"
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#include "sky-device.h"
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/* External functions */
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void pke0_attach(SIM_DESC sd);
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void pke0_issue(SIM_DESC sd);
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void pke1_attach(SIM_DESC sd);
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void pke1_issue(SIM_DESC sd);
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/* structs declared below */
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struct pke_fifo;
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struct fifo_quadword;
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/* Quadword data type */
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typedef unsigned_4 quadword[4];
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/* truncate address to quadword */
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#define ADDR_TRUNC_QW(addr) ((addr) & ~0x0f)
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/* extract offset in quadword */
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#define ADDR_OFFSET_QW(addr) ((addr) & 0x0f)
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/* SCEI memory mapping information */
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#define PKE0_REGISTER_WINDOW_START 0x10003800
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#define PKE1_REGISTER_WINDOW_START 0x10003C00
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#define PKE0_FIFO_ADDR 0x10004000
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#define PKE1_FIFO_ADDR 0x10005000
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/* VU source-addr tracking tables */ /* changed from 1998-01-22 e-mail plans */
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#define VU0_MEM0_SRCADDR_START 0x21000000
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#define VU0_MEM1_SRCADDR_START 0x21004000
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#define VU1_MEM0_SRCADDR_START 0x21008000
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#define VU1_MEM1_SRCADDR_START 0x2100C000
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#define VU0_CIA (VU0_REGISTER_WINDOW_START + VU_REG_CIA)
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#define VU1_CIA (VU1_REGISTER_WINDOW_START + VU_REG_CIA)
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/* GPUIF STAT register */
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#define GPUIF_REG_STAT_APATH_E 11
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#define GPUIF_REG_STAT_APATH_B 10
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/* COP2 STAT register */
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#define COP2_REG_STAT_ADDR VPU_STAT
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#define COP2_REG_STAT_VBS1_E 8
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#define COP2_REG_STAT_VBS1_B 8
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#define COP2_REG_STAT_VBS0_E 0
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#define COP2_REG_STAT_VBS0_B 0
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/* Quadword indices of PKE registers. Actual registers sit at bottom
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32 bits of each quadword. */
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#define PKE_REG_STAT 0x00
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#define PKE_REG_FBRST 0x01
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#define PKE_REG_ERR 0x02
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#define PKE_REG_MARK 0x03
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#define PKE_REG_CYCLE 0x04
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#define PKE_REG_MODE 0x05
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#define PKE_REG_NUM 0x06
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#define PKE_REG_MASK 0x07
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#define PKE_REG_CODE 0x08
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#define PKE_REG_ITOPS 0x09
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#define PKE_REG_BASE 0x0a /* pke1 only */
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#define PKE_REG_OFST 0x0b /* pke1 only */
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#define PKE_REG_TOPS 0x0c /* pke1 only */
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#define PKE_REG_ITOP 0x0d
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#define PKE_REG_TOP 0x0e /* pke1 only */
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#define PKE_REG_DBF 0x0f /* pke1 only */
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#define PKE_REG_R0 0x10 /* R0 .. R3 must be contiguous */
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#define PKE_REG_R1 0x11
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#define PKE_REG_R2 0x12
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#define PKE_REG_R3 0x13
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#define PKE_REG_C0 0x14 /* C0 .. C3 must be contiguous */
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#define PKE_REG_C1 0x15
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#define PKE_REG_C2 0x16
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#define PKE_REG_C3 0x17
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/* one plus last index */
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#define PKE_NUM_REGS 0x18
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#define PKE_REGISTER_WINDOW_SIZE (sizeof(quadword) * PKE_NUM_REGS)
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/* PKE commands */
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#define PKE_CMD_PKENOP_MASK 0x7F
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#define PKE_CMD_PKENOP_BITS 0x00
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#define PKE_CMD_STCYCL_MASK 0x7F
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#define PKE_CMD_STCYCL_BITS 0x01
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#define PKE_CMD_OFFSET_MASK 0x7F
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#define PKE_CMD_OFFSET_BITS 0x02
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#define PKE_CMD_BASE_MASK 0x7F
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#define PKE_CMD_BASE_BITS 0x03
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#define PKE_CMD_ITOP_MASK 0x7F
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#define PKE_CMD_ITOP_BITS 0x04
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#define PKE_CMD_STMOD_MASK 0x7F
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#define PKE_CMD_STMOD_BITS 0x05
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#define PKE_CMD_MSKPATH3_MASK 0x7F
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#define PKE_CMD_MSKPATH3_BITS 0x06
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#define PKE_CMD_PKEMARK_MASK 0x7F
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#define PKE_CMD_PKEMARK_BITS 0x07
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#define PKE_CMD_FLUSHE_MASK 0x7F
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#define PKE_CMD_FLUSHE_BITS 0x10
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#define PKE_CMD_FLUSH_MASK 0x7F
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#define PKE_CMD_FLUSH_BITS 0x11
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#define PKE_CMD_FLUSHA_MASK 0x7F
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#define PKE_CMD_FLUSHA_BITS 0x13
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#define PKE_CMD_PKEMSCAL_MASK 0x7F /* CAL == "call" */
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#define PKE_CMD_PKEMSCAL_BITS 0x14
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#define PKE_CMD_PKEMSCNT_MASK 0x7F /* CNT == "continue" */
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#define PKE_CMD_PKEMSCNT_BITS 0x17
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#define PKE_CMD_PKEMSCALF_MASK 0x7F /* CALF == "call after flush" */
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#define PKE_CMD_PKEMSCALF_BITS 0x15
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#define PKE_CMD_STMASK_MASK 0x7F
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#define PKE_CMD_STMASK_BITS 0x20
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#define PKE_CMD_STROW_MASK 0x7F
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#define PKE_CMD_STROW_BITS 0x30
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#define PKE_CMD_STCOL_MASK 0x7F
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#define PKE_CMD_STCOL_BITS 0x31
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#define PKE_CMD_MPG_MASK 0x7F
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#define PKE_CMD_MPG_BITS 0x4A
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#define PKE_CMD_DIRECT_MASK 0x7F
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#define PKE_CMD_DIRECT_BITS 0x50
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#define PKE_CMD_DIRECTHL_MASK 0x7F
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#define PKE_CMD_DIRECTHL_BITS 0x51
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#define PKE_CMD_UNPACK_MASK 0x60
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#define PKE_CMD_UNPACK_BITS 0x60
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/* test given word for particular PKE command bit pattern */
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#define IS_PKE_CMD(word,cmd) (((word) & PKE_CMD_##cmd##_MASK) == PKE_CMD_##cmd##_BITS)
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/* register bitmasks: bit numbers for end and beginning of fields */
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/* PKE opcode */
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#define PKE_OPCODE_I_E 31
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#define PKE_OPCODE_I_B 31
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#define PKE_OPCODE_CMD_E 30
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#define PKE_OPCODE_CMD_B 24
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#define PKE_OPCODE_NUM_E 23
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#define PKE_OPCODE_NUM_B 16
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#define PKE_OPCODE_IMM_E 15
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#define PKE_OPCODE_IMM_B 0
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/* STAT register */
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#define PKE_REG_STAT_FQC_E 28
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#define PKE_REG_STAT_FQC_B 24
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#define PKE_REG_STAT_FDR_E 23
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#define PKE_REG_STAT_FDR_B 23
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#define PKE_REG_STAT_ER1_E 13
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#define PKE_REG_STAT_ER1_B 13
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#define PKE_REG_STAT_ER0_E 12
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#define PKE_REG_STAT_ER0_B 12
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#define PKE_REG_STAT_INT_E 11
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#define PKE_REG_STAT_INT_B 11
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#define PKE_REG_STAT_PIS_E 10
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#define PKE_REG_STAT_PIS_B 10
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#define PKE_REG_STAT_PFS_E 9
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#define PKE_REG_STAT_PFS_B 9
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#define PKE_REG_STAT_PSS_E 8
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#define PKE_REG_STAT_PSS_B 8
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#define PKE_REG_STAT_DBF_E 7
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#define PKE_REG_STAT_DBF_B 7
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#define PKE_REG_STAT_MRK_E 6
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#define PKE_REG_STAT_MRK_B 6
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#define PKE_REG_STAT_PGW_E 3
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#define PKE_REG_STAT_PGW_B 3
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#define PKE_REG_STAT_PEW_E 2
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#define PKE_REG_STAT_PEW_B 2
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#define PKE_REG_STAT_PPS_E 1
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#define PKE_REG_STAT_PPS_B 0
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#define PKE_REG_STAT_PPS_IDLE 0x00 /* ready to execute next instruction */
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#define PKE_REG_STAT_PPS_WAIT 0x01 /* not enough words in FIFO */
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#define PKE_REG_STAT_PPS_DECODE 0x02 /* decoding instruction */
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#define PKE_REG_STAT_PPS_STALL 0x02 /* alias state for stall (e.g., FLUSHE) */
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#define PKE_REG_STAT_PPS_XFER 0x03 /* transferring instruction operands */
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/* DBF register */
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#define PKE_REG_DBF_DF_E 0
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#define PKE_REG_DBF_DF_B 0
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/* OFST register */
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#define PKE_REG_OFST_OFFSET_E 9
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#define PKE_REG_OFST_OFFSET_B 0
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/* OFST register */
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#define PKE_REG_TOPS_TOPS_E 9
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#define PKE_REG_TOPS_TOPS_B 0
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/* BASE register */
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#define PKE_REG_BASE_BASE_E 9
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#define PKE_REG_BASE_BASE_B 0
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/* ITOPS register */
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#define PKE_REG_ITOPS_ITOPS_E 9
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#define PKE_REG_ITOPS_ITOPS_B 0
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/* MODE register */
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#define PKE_REG_MODE_MDE_E 1
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#define PKE_REG_MODE_MDE_B 0
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/* NUM register */
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#define PKE_REG_NUM_NUM_E 9
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#define PKE_REG_NUM_NUM_B 0
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/* MARK register */
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#define PKE_REG_MARK_MARK_E 15
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#define PKE_REG_MARK_MARK_B 0
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/* ITOP register */
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#define PKE_REG_ITOP_ITOP_E 9
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#define PKE_REG_ITOP_ITOP_B 0
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/* TOP register */
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#define PKE_REG_TOP_TOP_E 9
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#define PKE_REG_TOP_TOP_B 0
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/* MASK register */
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#define PKE_REG_MASK_MASK_E 31
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#define PKE_REG_MASK_MASK_B 0
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/* CYCLE register */
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#define PKE_REG_CYCLE_WL_E 15
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#define PKE_REG_CYCLE_WL_B 8
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#define PKE_REG_CYCLE_CL_E 7
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#define PKE_REG_CYCLE_CL_B 0
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/* ERR register */
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#define PKE_REG_ERR_ME1_E 2
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#define PKE_REG_ERR_ME1_B 2
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#define PKE_REG_ERR_ME0_E 1
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#define PKE_REG_ERR_ME0_B 1
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#define PKE_REG_ERR_MII_E 0
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#define PKE_REG_ERR_MII_B 0
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/* FBRST command bitfields */
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#define PKE_REG_FBRST_STC_E 3
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#define PKE_REG_FBRST_STC_B 3
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#define PKE_REG_FBRST_STP_E 2
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#define PKE_REG_FBRST_STP_B 2
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#define PKE_REG_FBRST_FBK_E 1
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#define PKE_REG_FBRST_FBK_B 1
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#define PKE_REG_FBRST_RST_E 0
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#define PKE_REG_FBRST_RST_B 0
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/* MSKPATH3 command bitfields */
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#define PKE_REG_MSKPATH3_E 15
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#define PKE_REG_MSKPATH3_B 15
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/* UNPACK opcodes */
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#define PKE_UNPACK(vn,vl) ((vn) << 2 | (vl))
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#define PKE_UNPACK_S_32 PKE_UNPACK(0, 0)
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#define PKE_UNPACK_S_16 PKE_UNPACK(0, 1)
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#define PKE_UNPACK_S_8 PKE_UNPACK(0, 2)
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#define PKE_UNPACK_V2_32 PKE_UNPACK(1, 0)
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#define PKE_UNPACK_V2_16 PKE_UNPACK(1, 1)
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#define PKE_UNPACK_V2_8 PKE_UNPACK(1, 2)
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#define PKE_UNPACK_V3_32 PKE_UNPACK(2, 0)
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#define PKE_UNPACK_V3_16 PKE_UNPACK(2, 1)
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#define PKE_UNPACK_V3_8 PKE_UNPACK(2, 2)
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#define PKE_UNPACK_V4_32 PKE_UNPACK(3, 0)
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#define PKE_UNPACK_V4_16 PKE_UNPACK(3, 1)
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#define PKE_UNPACK_V4_8 PKE_UNPACK(3, 2)
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#define PKE_UNPACK_V4_5 PKE_UNPACK(3, 3)
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/* MASK register sub-field definitions */
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#define PKE_MASKREG_INPUT 0
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#define PKE_MASKREG_ROW 1
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#define PKE_MASKREG_COLUMN 2
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#define PKE_MASKREG_NOTHING 3
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/* STMOD register field definitions */
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#define PKE_MODE_INPUT 0
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#define PKE_MODE_ADDROW 1
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#define PKE_MODE_ACCROW 2
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/* extract a MASK register sub-field for row [0..3] and column [0..3] */
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/* MASK register is laid out of 2-bit values in this r-c order */
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/* m33 m32 m31 m30 m23 m22 m21 m20 m13 m12 m11 m10 m03 m02 m01 m00 */
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#define PKE_MASKREG_GET(me,row,col) \
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((((me)->regs[PKE_REG_MASK][0]) >> (8*(row) + 2*(col))) & 0x03)
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/* operations - replace with those in sim-bits.h when convenient */
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/* unsigned 32-bit mask of given width */
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#define BIT_MASK(width) ((width) == 31 ? 0xffffffff : (((unsigned_4)1) << (width+1)) - 1)
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/* e.g.: BIT_MASK(4) = 00011111 */
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/* mask between given given bits numbers (MSB) */
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#define BIT_MASK_BTW(begin,end) ((BIT_MASK(end) & ~((begin) == 0 ? 0 : BIT_MASK((begin)-1))))
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/* e.g.: BIT_MASK_BTW(4,11) = 0000111111110000 */
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/* set bitfield value */
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#define BIT_MASK_SET(lvalue,begin,end,value) \
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do { \
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ASSERT((begin) <= (end)); \
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(lvalue) &= ~BIT_MASK_BTW((begin),(end)); \
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(lvalue) |= ((value) << (begin)) & BIT_MASK_BTW((begin),(end)); \
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} while(0)
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/* get bitfield value */
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#define BIT_MASK_GET(rvalue,begin,end) \
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(((rvalue) & BIT_MASK_BTW(begin,end)) >> (begin))
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/* e.g., BIT_MASK_GET(0000111100001111, 2, 8) = 0000000100001100 */
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/* These ugly macro hacks allow succinct bitfield accesses */
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/* set a bitfield in a register by "name" */
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#define PKE_REG_MASK_SET(me,reg,flag,value) \
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do { \
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unsigned_4 old = BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
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PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E); \
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BIT_MASK_SET(((me)->regs[PKE_REG_##reg][0]), \
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PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E, \
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(value)); \
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if((me)->fifo_trace_file != NULL) \
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{ \
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if(old != (value)) \
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fprintf((me)->fifo_trace_file, "# Reg %s:%s = 0x%x\n", #reg, #flag, (unsigned)(value)); \
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} \
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} while(0)
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/* get a bitfield from a register by "name" */
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#define PKE_REG_MASK_GET(me,reg,flag) \
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BIT_MASK_GET(((me)->regs[PKE_REG_##reg][0]), \
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PKE_REG_##reg##_##flag##_B, PKE_REG_##reg##_##flag##_E)
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#define PKE_LIMIT(value,max) ((value) > (max) ? (max) : (value))
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/* Classify words in a FIFO quadword */
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enum wordclass
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{
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wc_dma = 'D',
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wc_pkecode = 'P',
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wc_unknown = '?',
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wc_pkedata = '.',
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wc_gpuiftag = 'g'
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};
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/* One row in the FIFO */
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struct fifo_quadword
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{
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/* 128 bits of data */
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quadword data;
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/* source main memory address (or 0: unknown) */
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unsigned_4 source_address;
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/* classification of words in quadword; wc_dma set on DMA tags at FIFO write */
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enum wordclass word_class[4];
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};
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/* quadword FIFO structure for PKE */
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typedef struct pke_fifo
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{
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struct fifo_quadword** quadwords; /* pointer to fifo quadwords */
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unsigned_4 origin; /* quadword serial number of quadwords[0] */
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unsigned_4 length; /* length of quadword pointer array: 0..N */
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unsigned_4 next; /* relative index of first unfilled quadword: 0..length-1 */
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} pke_fifo;
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#define PKE_FIFO_GROW_SIZE 1000 /* number of quadword pointers to allocate */
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#define PKE_FIFO_ARCHEOLOGY 1000 /* number of old quadwords to keep as history */
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/* PKE internal state: FIFOs, registers, handle to VU friend */
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struct pke_device
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{
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/* common device info */
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device dev;
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/* identity: 0=PKE0, 1=PKE1 */
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int pke_number;
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int flags;
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/* quadword registers: data in [0] word only */
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quadword regs[PKE_NUM_REGS];
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/* write buffer for FIFO address */
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quadword fifo_qw_in_progress;
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int fifo_qw_done; /* bitfield */
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/* FIFO - private: use only pke_fifo_* routines to access */
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struct pke_fifo fifo; /* array of FIFO quadword pointers */
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FILE* fifo_trace_file; /* stdio stream open in append mode, or 0 for no trace */
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/* FIFO cache -- curry last search pke_pcrel_fifo results */
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unsigned_4 last_fifo_pc;
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unsigned_4 last_qw_pc;
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unsigned_4 last_num;
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unsigned_4 last_new_fifo_pc;
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unsigned_4 last_new_qw_pc;
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/* PC */
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int fifo_pc; /* 0 .. (fifo_num_elements-1): quadword index of next instruction */
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int qw_pc; /* 0 .. 3: word index of next instruction */
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};
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extern struct pke_device pke0_device;
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extern struct pke_device pke1_device;
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int read_pke_reg (struct pke_device *device, int regno, void *buf);
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int write_pke_reg (struct pke_device *device, int regno, const void *buf);
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int read_pke_pc (struct pke_device *device, void *buf);
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/* Flags for PKE.flags */
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#define PKE_FLAG_NONE 0x00
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#define PKE_FLAG_PENDING_PSS 0x01 /* PSS bit written-to; set STAT:PSS after current instruction */
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#define PKE_FLAG_INT_NOLOOP 0x02 /* INT PKEcode received; INT/PIS set; suppress loop after resumption */
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/* Kludge alert */
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#define PKE_MEM_READ(me,addr,data,size) \
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do { \
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sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
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unsigned_##size value = \
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sim_core_read_aligned_##size(cpu, CIA_GET(cpu), read_map, \
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(SIM_ADDR)(addr)); \
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memcpy((unsigned_##size*) (data), (void*) & value, size); \
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} while(0)
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#define PKE_MEM_WRITE(me,addr,data,size) \
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do { sim_cpu* cpu = STATE_CPU(CURRENT_STATE, 0); \
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unsigned_##size value; \
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memcpy((void*) & value, (unsigned_##size*)(data), size); \
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sim_core_write_aligned_##size(cpu, CIA_GET(cpu), write_map, \
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(SIM_ADDR)(addr), value); \
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if((me)->fifo_trace_file != NULL) \
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{ \
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int i; \
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unsigned_##size value_te; \
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value_te = H2T_##size(value); \
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fprintf((me)->fifo_trace_file, "# Write %2d bytes to ", size); \
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fprintf((me)->fifo_trace_file, "0x%08lx: ", (unsigned long)(addr)); \
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for(i=0; i<size; i++) \
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fprintf((me)->fifo_trace_file, " %02x", ((unsigned_1*)(& value_te))[i]); \
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fprintf((me)->fifo_trace_file, "\n"); \
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} \
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} while(0)
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#endif /* H_PKE_H */
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