mirror of
https://sourceware.org/git/binutils-gdb.git
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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
1175 lines
33 KiB
C
1175 lines
33 KiB
C
/* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
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/* CPU data for lm32.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright (C) 1996-2024 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and/or GDB, the GNU debugger.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include "sysdep.h"
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#include <stdio.h>
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#include <stdarg.h>
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#include <stdlib.h>
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#include "ansidecl.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "lm32-desc.h"
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#include "lm32-opc.h"
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#include "opintl.h"
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#include "libiberty.h"
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#include "xregex.h"
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/* Attributes. */
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static const CGEN_ATTR_ENTRY bool_attr[] =
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{
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{ "#f", 0 },
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{ "#t", 1 },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
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{
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{ "base", MACH_BASE },
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{ "lm32", MACH_LM32 },
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{ "max", MACH_MAX },
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{ 0, 0 }
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};
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static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
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{
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{ "lm32", ISA_LM32 },
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{ "max", ISA_MAX },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE lm32_cgen_ifield_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "RESERVED", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE lm32_cgen_hardware_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "PC", &bool_attr[0], &bool_attr[0] },
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{ "PROFILE", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE lm32_cgen_operand_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
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{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
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{ "SIGNED", &bool_attr[0], &bool_attr[0] },
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{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
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{ "RELAX", &bool_attr[0], &bool_attr[0] },
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{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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const CGEN_ATTR_TABLE lm32_cgen_insn_attr_table[] =
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{
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{ "MACH", & MACH_attr[0], & MACH_attr[0] },
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{ "ALIAS", &bool_attr[0], &bool_attr[0] },
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{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
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{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
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{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
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{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
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{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
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{ "RELAXED", &bool_attr[0], &bool_attr[0] },
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{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
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{ "PBB", &bool_attr[0], &bool_attr[0] },
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{ 0, 0, 0 }
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};
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/* Instruction set variants. */
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static const CGEN_ISA lm32_cgen_isa_table[] = {
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{ "lm32", 32, 32, 32, 32 },
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{ 0, 0, 0, 0, 0 }
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};
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/* Machine variants. */
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static const CGEN_MACH lm32_cgen_mach_table[] = {
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{ "lm32", "lm32", MACH_LM32, 0 },
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{ 0, 0, 0, 0 }
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};
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static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_gr_entries[] =
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{
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{ "gp", 26, {0, {{{0, 0}}}}, 0, 0 },
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{ "fp", 27, {0, {{{0, 0}}}}, 0, 0 },
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{ "sp", 28, {0, {{{0, 0}}}}, 0, 0 },
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{ "ra", 29, {0, {{{0, 0}}}}, 0, 0 },
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{ "ea", 30, {0, {{{0, 0}}}}, 0, 0 },
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{ "ba", 31, {0, {{{0, 0}}}}, 0, 0 },
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{ "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
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{ "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
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{ "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
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{ "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
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{ "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
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{ "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
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{ "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
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{ "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
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{ "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
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{ "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
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{ "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
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{ "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
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{ "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
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{ "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
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{ "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
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{ "r16", 16, {0, {{{0, 0}}}}, 0, 0 },
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{ "r17", 17, {0, {{{0, 0}}}}, 0, 0 },
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{ "r18", 18, {0, {{{0, 0}}}}, 0, 0 },
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{ "r19", 19, {0, {{{0, 0}}}}, 0, 0 },
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{ "r20", 20, {0, {{{0, 0}}}}, 0, 0 },
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{ "r21", 21, {0, {{{0, 0}}}}, 0, 0 },
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{ "r22", 22, {0, {{{0, 0}}}}, 0, 0 },
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{ "r23", 23, {0, {{{0, 0}}}}, 0, 0 },
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{ "r24", 24, {0, {{{0, 0}}}}, 0, 0 },
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{ "r25", 25, {0, {{{0, 0}}}}, 0, 0 },
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{ "r26", 26, {0, {{{0, 0}}}}, 0, 0 },
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{ "r27", 27, {0, {{{0, 0}}}}, 0, 0 },
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{ "r28", 28, {0, {{{0, 0}}}}, 0, 0 },
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{ "r29", 29, {0, {{{0, 0}}}}, 0, 0 },
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{ "r30", 30, {0, {{{0, 0}}}}, 0, 0 },
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{ "r31", 31, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD lm32_cgen_opval_h_gr =
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{
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& lm32_cgen_opval_h_gr_entries[0],
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38,
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0, 0, 0, 0, ""
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};
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static CGEN_KEYWORD_ENTRY lm32_cgen_opval_h_csr_entries[] =
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{
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{ "IE", 0, {0, {{{0, 0}}}}, 0, 0 },
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{ "IM", 1, {0, {{{0, 0}}}}, 0, 0 },
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{ "IP", 2, {0, {{{0, 0}}}}, 0, 0 },
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{ "ICC", 3, {0, {{{0, 0}}}}, 0, 0 },
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{ "DCC", 4, {0, {{{0, 0}}}}, 0, 0 },
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{ "CC", 5, {0, {{{0, 0}}}}, 0, 0 },
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{ "CFG", 6, {0, {{{0, 0}}}}, 0, 0 },
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{ "EBA", 7, {0, {{{0, 0}}}}, 0, 0 },
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{ "DC", 8, {0, {{{0, 0}}}}, 0, 0 },
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{ "DEBA", 9, {0, {{{0, 0}}}}, 0, 0 },
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{ "CFG2", 10, {0, {{{0, 0}}}}, 0, 0 },
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{ "JTX", 14, {0, {{{0, 0}}}}, 0, 0 },
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{ "JRX", 15, {0, {{{0, 0}}}}, 0, 0 },
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{ "BP0", 16, {0, {{{0, 0}}}}, 0, 0 },
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{ "BP1", 17, {0, {{{0, 0}}}}, 0, 0 },
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{ "BP2", 18, {0, {{{0, 0}}}}, 0, 0 },
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{ "BP3", 19, {0, {{{0, 0}}}}, 0, 0 },
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{ "WP0", 24, {0, {{{0, 0}}}}, 0, 0 },
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{ "WP1", 25, {0, {{{0, 0}}}}, 0, 0 },
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{ "WP2", 26, {0, {{{0, 0}}}}, 0, 0 },
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{ "WP3", 27, {0, {{{0, 0}}}}, 0, 0 },
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{ "PSW", 29, {0, {{{0, 0}}}}, 0, 0 },
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{ "TLBVADDR", 30, {0, {{{0, 0}}}}, 0, 0 },
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{ "TLBPADDR", 31, {0, {{{0, 0}}}}, 0, 0 },
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{ "TLBBADVADDR", 31, {0, {{{0, 0}}}}, 0, 0 }
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};
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CGEN_KEYWORD lm32_cgen_opval_h_csr =
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{
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& lm32_cgen_opval_h_csr_entries[0],
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25,
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0, 0, 0, 0, ""
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};
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/* The hardware table. */
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#define A(a) (1 << CGEN_HW_##a)
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const CGEN_HW_ENTRY lm32_cgen_hw_table[] =
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{
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{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_gr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, & lm32_cgen_opval_h_csr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
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};
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#undef A
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/* The instruction field table. */
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#define A(a) (1 << CGEN_IFLD_##a)
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const CGEN_IFLD lm32_cgen_ifld_table[] =
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{
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{ LM32_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_R0, "f-r0", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_R1, "f-r1", 0, 32, 20, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_R2, "f-r2", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_RESV0, "f-resv0", 0, 32, 10, 11, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_SHIFT, "f-shift", 0, 32, 4, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_UIMM, "f-uimm", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_CSR, "f-csr", 0, 32, 25, 5, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_USER, "f-user", 0, 32, 10, 11, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_EXCEPTION, "f-exception", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_BRANCH, "f-branch", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
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{ LM32_F_CALL, "f-call", 0, 32, 25, 26, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
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{ 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
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};
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#undef A
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/* multi ifield declarations */
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/* multi ifield definitions */
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/* The operand table. */
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#define A(a) (1 << CGEN_OPERAND_##a)
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#define OPERAND(op) LM32_OPERAND_##op
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const CGEN_OPERAND lm32_cgen_operand_table[] =
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{
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/* pc: program counter */
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{ "pc", LM32_OPERAND_PC, HW_H_PC, 0, 0,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_NIL] } },
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{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
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/* r0: register 0 */
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{ "r0", LM32_OPERAND_R0, HW_H_GR, 25, 5,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_R0] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* r1: register 1 */
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{ "r1", LM32_OPERAND_R1, HW_H_GR, 20, 5,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_R1] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* r2: register 2 */
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{ "r2", LM32_OPERAND_R2, HW_H_GR, 15, 5,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_R2] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* shift: shift amout */
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{ "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_SHIFT] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* imm: signed immediate */
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{ "imm", LM32_OPERAND_IMM, HW_H_SINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* uimm: unsigned immediate */
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{ "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* branch: branch offset */
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{ "branch", LM32_OPERAND_BRANCH, HW_H_IADDR, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_BRANCH] } },
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{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
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/* call: call offset */
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{ "call", LM32_OPERAND_CALL, HW_H_IADDR, 25, 26,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_CALL] } },
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{ 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
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/* csr: csr */
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{ "csr", LM32_OPERAND_CSR, HW_H_CSR, 25, 5,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_CSR] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* user: user */
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{ "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_USER] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* exception: exception */
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{ "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_EXCEPTION] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* hi16: high 16-bit immediate */
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{ "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* lo16: low 16-bit immediate */
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{ "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_UIMM] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* gp16: gp relative 16-bit immediate */
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{ "gp16", LM32_OPERAND_GP16, HW_H_SINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
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{ 0, { { { (1<<MACH_BASE), 0 } } } } },
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/* got16: got 16-bit immediate */
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{ "got16", LM32_OPERAND_GOT16, HW_H_SINT, 15, 16,
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{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
|
|
/* gotoffhi16: got offset high 16-bit immediate */
|
|
{ "gotoffhi16", LM32_OPERAND_GOTOFFHI16, HW_H_SINT, 15, 16,
|
|
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
|
|
/* gotofflo16: got offset low 16-bit immediate */
|
|
{ "gotofflo16", LM32_OPERAND_GOTOFFLO16, HW_H_SINT, 15, 16,
|
|
{ 0, { &lm32_cgen_ifld_table[LM32_F_IMM] } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
|
|
/* sentinel */
|
|
{ 0, 0, 0, 0, 0,
|
|
{ 0, { 0 } },
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
|
|
};
|
|
|
|
#undef A
|
|
|
|
|
|
/* The instruction table. */
|
|
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
#define A(a) (1 << CGEN_INSN_##a)
|
|
|
|
static const CGEN_IBASE lm32_cgen_insn_table[MAX_INSNS] =
|
|
{
|
|
/* Special null first entry.
|
|
A `num' value of zero is thus invalid.
|
|
Also, the special `invalid' insn resides here. */
|
|
{ 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
|
|
/* add $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_ADD, "add", "add", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* addi $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_ADDI, "addi", "addi", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* and $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_AND, "and", "and", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* andi $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_ANDI, "andi", "andi", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* andhi $r1,$r0,$hi16 */
|
|
{
|
|
LM32_INSN_ANDHII, "andhii", "andhi", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* b $r0 */
|
|
{
|
|
LM32_INSN_B, "b", "b", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bi $call */
|
|
{
|
|
LM32_INSN_BI, "bi", "bi", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* be $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BE, "be", "be", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bg $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BG, "bg", "bg", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bge $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BGE, "bge", "bge", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bgeu $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BGEU, "bgeu", "bgeu", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bgu $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BGU, "bgu", "bgu", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bne $r0,$r1,$branch */
|
|
{
|
|
LM32_INSN_BNE, "bne", "bne", 32,
|
|
{ 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* call $r0 */
|
|
{
|
|
LM32_INSN_CALL, "call", "call", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* calli $call */
|
|
{
|
|
LM32_INSN_CALLI, "calli", "calli", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpe $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPE, "cmpe", "cmpe", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpei $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_CMPEI, "cmpei", "cmpei", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpg $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPG, "cmpg", "cmpg", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgi $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_CMPGI, "cmpgi", "cmpgi", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpge $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPGE, "cmpge", "cmpge", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgei $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_CMPGEI, "cmpgei", "cmpgei", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgeu $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPGEU, "cmpgeu", "cmpgeu", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgeui $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_CMPGEUI, "cmpgeui", "cmpgeui", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgu $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPGU, "cmpgu", "cmpgu", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpgui $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_CMPGUI, "cmpgui", "cmpgui", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpne $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_CMPNE, "cmpne", "cmpne", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* cmpnei $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_CMPNEI, "cmpnei", "cmpnei", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* divu $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_DIVU, "divu", "divu", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lb $r1,($r0+$imm) */
|
|
{
|
|
LM32_INSN_LB, "lb", "lb", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lbu $r1,($r0+$imm) */
|
|
{
|
|
LM32_INSN_LBU, "lbu", "lbu", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lh $r1,($r0+$imm) */
|
|
{
|
|
LM32_INSN_LH, "lh", "lh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lhu $r1,($r0+$imm) */
|
|
{
|
|
LM32_INSN_LHU, "lhu", "lhu", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lw $r1,($r0+$imm) */
|
|
{
|
|
LM32_INSN_LW, "lw", "lw", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* modu $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_MODU, "modu", "modu", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mul $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_MUL, "mul", "mul", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* muli $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_MULI, "muli", "muli", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* nor $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_NOR, "nor", "nor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* nori $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_NORI, "nori", "nori", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* or $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_OR, "or", "or", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* ori $r1,$r0,$lo16 */
|
|
{
|
|
LM32_INSN_ORI, "ori", "ori", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* orhi $r1,$r0,$hi16 */
|
|
{
|
|
LM32_INSN_ORHII, "orhii", "orhi", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* rcsr $r2,$csr */
|
|
{
|
|
LM32_INSN_RCSR, "rcsr", "rcsr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sb ($r0+$imm),$r1 */
|
|
{
|
|
LM32_INSN_SB, "sb", "sb", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sextb $r2,$r0 */
|
|
{
|
|
LM32_INSN_SEXTB, "sextb", "sextb", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sexth $r2,$r0 */
|
|
{
|
|
LM32_INSN_SEXTH, "sexth", "sexth", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sh ($r0+$imm),$r1 */
|
|
{
|
|
LM32_INSN_SH, "sh", "sh", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sl $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_SL, "sl", "sl", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sli $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_SLI, "sli", "sli", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sr $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_SR, "sr", "sr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sri $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_SRI, "sri", "sri", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sru $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_SRU, "sru", "sru", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* srui $r1,$r0,$imm */
|
|
{
|
|
LM32_INSN_SRUI, "srui", "srui", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sub $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_SUB, "sub", "sub", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sw ($r0+$imm),$r1 */
|
|
{
|
|
LM32_INSN_SW, "sw", "sw", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* user $r2,$r0,$r1,$user */
|
|
{
|
|
LM32_INSN_USER, "user", "user", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* wcsr $csr,$r1 */
|
|
{
|
|
LM32_INSN_WCSR, "wcsr", "wcsr", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* xor $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_XOR, "xor", "xor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* xori $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_XORI, "xori", "xori", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* xnor $r2,$r0,$r1 */
|
|
{
|
|
LM32_INSN_XNOR, "xnor", "xnor", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* xnori $r1,$r0,$uimm */
|
|
{
|
|
LM32_INSN_XNORI, "xnori", "xnori", 32,
|
|
{ 0, { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* break */
|
|
{
|
|
LM32_INSN_BREAK, "break", "break", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* scall */
|
|
{
|
|
LM32_INSN_SCALL, "scall", "scall", 32,
|
|
{ 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* bret */
|
|
{
|
|
-1, "bret", "bret", 32,
|
|
{ 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* eret */
|
|
{
|
|
-1, "eret", "eret", 32,
|
|
{ 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* ret */
|
|
{
|
|
-1, "ret", "ret", 32,
|
|
{ 0|A(ALIAS)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mv $r2,$r0 */
|
|
{
|
|
-1, "mv", "mv", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mvi $r1,$imm */
|
|
{
|
|
-1, "mvi", "mvi", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mvu $r1,$lo16 */
|
|
{
|
|
-1, "mvui", "mvu", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mvhi $r1,$hi16 */
|
|
{
|
|
-1, "mvhi", "mvhi", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* mva $r1,$gp16 */
|
|
{
|
|
-1, "mva", "mva", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* not $r2,$r0 */
|
|
{
|
|
-1, "not", "not", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* nop */
|
|
{
|
|
-1, "nop", "nop", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lb $r1,$gp16 */
|
|
{
|
|
-1, "lbgprel", "lb", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lbu $r1,$gp16 */
|
|
{
|
|
-1, "lbugprel", "lbu", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lh $r1,$gp16 */
|
|
{
|
|
-1, "lhgprel", "lh", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lhu $r1,$gp16 */
|
|
{
|
|
-1, "lhugprel", "lhu", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lw $r1,$gp16 */
|
|
{
|
|
-1, "lwgprel", "lw", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sb $gp16,$r1 */
|
|
{
|
|
-1, "sbgprel", "sb", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sh $gp16,$r1 */
|
|
{
|
|
-1, "shgprel", "sh", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sw $gp16,$r1 */
|
|
{
|
|
-1, "swgprel", "sw", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lw $r1,(gp+$got16) */
|
|
{
|
|
-1, "lwgotrel", "lw", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* orhi $r1,$r0,$gotoffhi16 */
|
|
{
|
|
-1, "orhigotoffi", "orhi", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* addi $r1,$r0,$gotofflo16 */
|
|
{
|
|
-1, "addgotoff", "addi", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sw ($r0+$gotofflo16),$r1 */
|
|
{
|
|
-1, "swgotoff", "sw", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lw $r1,($r0+$gotofflo16) */
|
|
{
|
|
-1, "lwgotoff", "lw", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sh ($r0+$gotofflo16),$r1 */
|
|
{
|
|
-1, "shgotoff", "sh", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lh $r1,($r0+$gotofflo16) */
|
|
{
|
|
-1, "lhgotoff", "lh", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lhu $r1,($r0+$gotofflo16) */
|
|
{
|
|
-1, "lhugotoff", "lhu", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* sb ($r0+$gotofflo16),$r1 */
|
|
{
|
|
-1, "sbgotoff", "sb", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lb $r1,($r0+$gotofflo16) */
|
|
{
|
|
-1, "lbgotoff", "lb", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
/* lbu $r1,($r0+$gotofflo16) */
|
|
{
|
|
-1, "lbugotoff", "lbu", 32,
|
|
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
|
},
|
|
};
|
|
|
|
#undef OP
|
|
#undef A
|
|
|
|
/* Initialize anything needed to be done once, before any cpu_open call. */
|
|
|
|
static void
|
|
init_tables (void)
|
|
{
|
|
}
|
|
|
|
#ifndef opcodes_error_handler
|
|
#define opcodes_error_handler(...) \
|
|
fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
|
|
#endif
|
|
|
|
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
|
|
static void build_hw_table (CGEN_CPU_TABLE *);
|
|
static void build_ifield_table (CGEN_CPU_TABLE *);
|
|
static void build_operand_table (CGEN_CPU_TABLE *);
|
|
static void build_insn_table (CGEN_CPU_TABLE *);
|
|
static void lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *);
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to look up a mach via its bfd name. */
|
|
|
|
static const CGEN_MACH *
|
|
lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
|
|
{
|
|
while (table->name)
|
|
{
|
|
if (strcmp (name, table->bfd_name) == 0)
|
|
return table;
|
|
++table;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_hw_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_HW_ENTRY *init = & lm32_cgen_hw_table[0];
|
|
/* MAX_HW is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_HW_ENTRY **selected =
|
|
(const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
|
|
cd->hw_table.init_entries = init;
|
|
cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
|
|
memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
|
|
/* ??? For now we just use machs to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->hw_table.entries = selected;
|
|
cd->hw_table.num_entries = MAX_HW;
|
|
}
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_ifield_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
cd->ifld_table = & lm32_cgen_ifld_table[0];
|
|
}
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to build the hardware table. */
|
|
|
|
static void
|
|
build_operand_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
int machs = cd->machs;
|
|
const CGEN_OPERAND *init = & lm32_cgen_operand_table[0];
|
|
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
|
|
However each entry is indexed by it's enum so there can be holes in
|
|
the table. */
|
|
const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
|
|
|
|
cd->operand_table.init_entries = init;
|
|
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
|
|
memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
|
|
/* ??? For now we just use mach to determine which ones we want. */
|
|
for (i = 0; init[i].name != NULL; ++i)
|
|
if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
|
|
& machs)
|
|
selected[init[i].type] = &init[i];
|
|
cd->operand_table.entries = selected;
|
|
cd->operand_table.num_entries = MAX_OPERANDS;
|
|
}
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to build the hardware table.
|
|
??? This could leave out insns not supported by the specified mach/isa,
|
|
but that would cause errors like "foo only supported by bar" to become
|
|
"unknown insn", so for now we include all insns and require the app to
|
|
do the checking later.
|
|
??? On the other hand, parsing of such insns may require their hardware or
|
|
operand elements to be in the table [which they mightn't be]. */
|
|
|
|
static void
|
|
build_insn_table (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
const CGEN_IBASE *ib = & lm32_cgen_insn_table[0];
|
|
CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
|
|
|
|
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
|
|
for (i = 0; i < MAX_INSNS; ++i)
|
|
insns[i].base = &ib[i];
|
|
cd->insn_table.init_entries = insns;
|
|
cd->insn_table.entry_size = sizeof (CGEN_IBASE);
|
|
cd->insn_table.num_init_entries = MAX_INSNS;
|
|
}
|
|
|
|
/* Subroutine of lm32_cgen_cpu_open to rebuild the tables. */
|
|
|
|
static void
|
|
lm32_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
|
|
{
|
|
int i;
|
|
CGEN_BITSET *isas = cd->isas;
|
|
unsigned int machs = cd->machs;
|
|
|
|
cd->int_insn_p = CGEN_INT_INSN_P;
|
|
|
|
/* Data derived from the isa spec. */
|
|
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
|
|
cd->default_insn_bitsize = UNSET;
|
|
cd->base_insn_bitsize = UNSET;
|
|
cd->min_insn_bitsize = 65535; /* Some ridiculously big number. */
|
|
cd->max_insn_bitsize = 0;
|
|
for (i = 0; i < MAX_ISAS; ++i)
|
|
if (cgen_bitset_contains (isas, i))
|
|
{
|
|
const CGEN_ISA *isa = & lm32_cgen_isa_table[i];
|
|
|
|
/* Default insn sizes of all selected isas must be
|
|
equal or we set the result to 0, meaning "unknown". */
|
|
if (cd->default_insn_bitsize == UNSET)
|
|
cd->default_insn_bitsize = isa->default_insn_bitsize;
|
|
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
|
|
; /* This is ok. */
|
|
else
|
|
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Base insn sizes of all selected isas must be equal
|
|
or we set the result to 0, meaning "unknown". */
|
|
if (cd->base_insn_bitsize == UNSET)
|
|
cd->base_insn_bitsize = isa->base_insn_bitsize;
|
|
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
|
|
; /* This is ok. */
|
|
else
|
|
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
|
|
|
|
/* Set min,max insn sizes. */
|
|
if (isa->min_insn_bitsize < cd->min_insn_bitsize)
|
|
cd->min_insn_bitsize = isa->min_insn_bitsize;
|
|
if (isa->max_insn_bitsize > cd->max_insn_bitsize)
|
|
cd->max_insn_bitsize = isa->max_insn_bitsize;
|
|
}
|
|
|
|
/* Data derived from the mach spec. */
|
|
for (i = 0; i < MAX_MACHS; ++i)
|
|
if (((1 << i) & machs) != 0)
|
|
{
|
|
const CGEN_MACH *mach = & lm32_cgen_mach_table[i];
|
|
|
|
if (mach->insn_chunk_bitsize != 0)
|
|
{
|
|
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
|
|
{
|
|
opcodes_error_handler
|
|
(/* xgettext:c-format */
|
|
_("internal error: lm32_cgen_rebuild_tables: "
|
|
"conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
|
|
cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
|
|
abort ();
|
|
}
|
|
|
|
cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
|
|
}
|
|
}
|
|
|
|
/* Determine which hw elements are used by MACH. */
|
|
build_hw_table (cd);
|
|
|
|
/* Build the ifield table. */
|
|
build_ifield_table (cd);
|
|
|
|
/* Determine which operands are used by MACH/ISA. */
|
|
build_operand_table (cd);
|
|
|
|
/* Build the instruction table. */
|
|
build_insn_table (cd);
|
|
}
|
|
|
|
/* Initialize a cpu table and return a descriptor.
|
|
It's much like opening a file, and must be the first function called.
|
|
The arguments are a set of (type/value) pairs, terminated with
|
|
CGEN_CPU_OPEN_END.
|
|
|
|
Currently supported values:
|
|
CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
|
|
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
|
|
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
|
|
CGEN_CPU_OPEN_ENDIAN: specify endian choice
|
|
CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
|
|
CGEN_CPU_OPEN_END: terminates arguments
|
|
|
|
??? Simultaneous multiple isas might not make sense, but it's not (yet)
|
|
precluded. */
|
|
|
|
CGEN_CPU_DESC
|
|
lm32_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
|
|
{
|
|
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
|
|
static int init_p;
|
|
CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
|
|
unsigned int machs = 0; /* 0 = "unspecified" */
|
|
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
|
|
enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
|
|
va_list ap;
|
|
|
|
if (! init_p)
|
|
{
|
|
init_tables ();
|
|
init_p = 1;
|
|
}
|
|
|
|
memset (cd, 0, sizeof (*cd));
|
|
|
|
va_start (ap, arg_type);
|
|
while (arg_type != CGEN_CPU_OPEN_END)
|
|
{
|
|
switch (arg_type)
|
|
{
|
|
case CGEN_CPU_OPEN_ISAS :
|
|
isas = va_arg (ap, CGEN_BITSET *);
|
|
break;
|
|
case CGEN_CPU_OPEN_MACHS :
|
|
machs = va_arg (ap, unsigned int);
|
|
break;
|
|
case CGEN_CPU_OPEN_BFDMACH :
|
|
{
|
|
const char *name = va_arg (ap, const char *);
|
|
const CGEN_MACH *mach =
|
|
lookup_mach_via_bfd_name (lm32_cgen_mach_table, name);
|
|
|
|
if (mach != NULL)
|
|
machs |= 1 << mach->num;
|
|
break;
|
|
}
|
|
case CGEN_CPU_OPEN_ENDIAN :
|
|
endian = va_arg (ap, enum cgen_endian);
|
|
break;
|
|
case CGEN_CPU_OPEN_INSN_ENDIAN :
|
|
insn_endian = va_arg (ap, enum cgen_endian);
|
|
break;
|
|
default :
|
|
opcodes_error_handler
|
|
(/* xgettext:c-format */
|
|
_("internal error: lm32_cgen_cpu_open: "
|
|
"unsupported argument `%d'"),
|
|
arg_type);
|
|
abort (); /* ??? return NULL? */
|
|
}
|
|
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
|
|
}
|
|
va_end (ap);
|
|
|
|
/* Mach unspecified means "all". */
|
|
if (machs == 0)
|
|
machs = (1 << MAX_MACHS) - 1;
|
|
/* Base mach is always selected. */
|
|
machs |= 1;
|
|
if (endian == CGEN_ENDIAN_UNKNOWN)
|
|
{
|
|
/* ??? If target has only one, could have a default. */
|
|
opcodes_error_handler
|
|
(/* xgettext:c-format */
|
|
_("internal error: lm32_cgen_cpu_open: no endianness specified"));
|
|
abort ();
|
|
}
|
|
|
|
cd->isas = cgen_bitset_copy (isas);
|
|
cd->machs = machs;
|
|
cd->endian = endian;
|
|
cd->insn_endian
|
|
= (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
|
|
|
|
/* Table (re)builder. */
|
|
cd->rebuild_tables = lm32_cgen_rebuild_tables;
|
|
lm32_cgen_rebuild_tables (cd);
|
|
|
|
/* Default to not allowing signed overflow. */
|
|
cd->signed_overflow_ok_p = 0;
|
|
|
|
return (CGEN_CPU_DESC) cd;
|
|
}
|
|
|
|
/* Cover fn to lm32_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
|
|
MACH_NAME is the bfd name of the mach. */
|
|
|
|
CGEN_CPU_DESC
|
|
lm32_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
|
|
{
|
|
return lm32_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
|
|
CGEN_CPU_OPEN_ENDIAN, endian,
|
|
CGEN_CPU_OPEN_END);
|
|
}
|
|
|
|
/* Close a cpu table.
|
|
??? This can live in a machine independent file, but there's currently
|
|
no place to put this file (there's no libcgen). libopcodes is the wrong
|
|
place as some simulator ports use this but they don't use libopcodes. */
|
|
|
|
void
|
|
lm32_cgen_cpu_close (CGEN_CPU_DESC cd)
|
|
{
|
|
unsigned int i;
|
|
const CGEN_INSN *insns;
|
|
|
|
if (cd->macro_insn_table.init_entries)
|
|
{
|
|
insns = cd->macro_insn_table.init_entries;
|
|
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
|
|
if (CGEN_INSN_RX ((insns)))
|
|
regfree (CGEN_INSN_RX (insns));
|
|
}
|
|
|
|
if (cd->insn_table.init_entries)
|
|
{
|
|
insns = cd->insn_table.init_entries;
|
|
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
|
|
if (CGEN_INSN_RX (insns))
|
|
regfree (CGEN_INSN_RX (insns));
|
|
}
|
|
|
|
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
|
|
free ((CGEN_INSN *) cd->insn_table.init_entries);
|
|
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
|
|
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
|
|
free (cd);
|
|
}
|
|
|