mirror of
https://sourceware.org/git/binutils-gdb.git
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1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
61 lines
1.7 KiB
C
61 lines
1.7 KiB
C
/* aarch64-sim.h -- Internal aarch64 settings.
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Copyright (C) 2015-2024 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef AARCH64_SIM_H
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#define AARCH64_SIM_H
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#include <stdint.h>
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#include "cpustate.h"
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/* A per-core state structure. */
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struct aarch64_sim_cpu
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{
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GRegister gr[33]; /* Extra register at index 32 is used to hold zero value. */
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FRegister fr[32];
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uint64_t pc;
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uint32_t CPSR;
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uint32_t FPSR; /* Floating point Status register. */
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uint32_t FPCR; /* Floating point Control register. */
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uint64_t nextpc;
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uint32_t instr;
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uint64_t tpidr; /* Thread pointer id. */
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};
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#define AARCH64_SIM_CPU(cpu) ((struct aarch64_sim_cpu *) CPU_ARCH_DATA (cpu))
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typedef enum
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{
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AARCH64_MIN_GR = 0,
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AARCH64_MAX_GR = 31,
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AARCH64_MIN_FR = 32,
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AARCH64_MAX_FR = 63,
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AARCH64_PC_REGNO = 64,
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AARCH64_CPSR_REGNO = 65,
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AARCH64_FPSR_REGNO = 66,
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AARCH64_MAX_REGNO = 67
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} aarch64_regno;
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#endif /* AARCH64_SIM_H */
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