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e73434e38f
Currently, the ravenscar-thread implementation for each architecture is written by hand. However, these are actually written by copy-paste. It seems better to switch to a table-driven approach. The previous code also fetched all registers whenever any register was requested. This is corrected in the new implementation.
64 lines
2.1 KiB
C
64 lines
2.1 KiB
C
/* Ravenscar SPARC target support.
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Copyright (C) 2004-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "gdbcore.h"
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#include "regcache.h"
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#include "sparc-tdep.h"
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#include "inferior.h"
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#include "ravenscar-thread.h"
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#include "sparc-ravenscar-thread.h"
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#include "gdbarch.h"
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/* Register offsets from a referenced address (exempli gratia the
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Thread_Descriptor). The referenced address depends on the register
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number. The Thread_Descriptor layout and the stack layout are documented
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in the GNAT sources, in sparc-bb.h. */
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static const int sparc_register_offsets[] =
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{
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/* G0 - G7 */
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-1, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C,
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/* O0 - O7 */
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0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C,
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/* L0 - L7 */
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0x00, 0x04, 0x08, 0x0C, 0x10, 0x14, 0x18, 0x1C,
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/* I0 - I7 */
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0x20, 0x24, 0x28, 0x2C, 0x30, 0x34, 0x38, 0x3C,
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/* F0 - F31 */
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0x50, 0x54, 0x58, 0x5C, 0x60, 0x64, 0x68, 0x6C,
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0x70, 0x74, 0x78, 0x7C, 0x80, 0x84, 0x88, 0x8C,
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0x90, 0x94, 0x99, 0x9C, 0xA0, 0xA4, 0xA8, 0xAC,
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0xB0, 0xB4, 0xBB, 0xBC, 0xC0, 0xC4, 0xC8, 0xCC,
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/* Y PSR WIM TBR PC NPC FPSR CPSR */
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0x40, 0x20, 0x44, -1, 0x1C, -1, 0x4C, -1
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};
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static struct ravenscar_arch_ops sparc_ravenscar_ops (sparc_register_offsets,
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SPARC_L0_REGNUM,
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SPARC_I7_REGNUM);
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/* Register ravenscar_arch_ops in GDBARCH. */
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void
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register_sparc_ravenscar_ops (struct gdbarch *gdbarch)
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{
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set_gdbarch_ravenscar_ops (gdbarch, &sparc_ravenscar_ops);
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}
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