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4a94e36819
This commit brings all the changes made by running gdb/copyright.py as per GDB's Start of New Year Procedure. For the avoidance of doubt, all changes in this commits were performed by the script.
219 lines
6.7 KiB
C
219 lines
6.7 KiB
C
/* Target-dependent code for FreeBSD on RISC-V processors.
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Copyright (C) 2018-2022 Free Software Foundation, Inc.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "fbsd-tdep.h"
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#include "osabi.h"
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#include "riscv-tdep.h"
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#include "riscv-fbsd-tdep.h"
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#include "solib-svr4.h"
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#include "target.h"
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#include "trad-frame.h"
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#include "tramp-frame.h"
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#include "gdbarch.h"
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#include "inferior.h"
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/* Register maps. */
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static const struct regcache_map_entry riscv_fbsd_gregmap[] =
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{
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{ 1, RISCV_RA_REGNUM, 0 },
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{ 1, RISCV_SP_REGNUM, 0 },
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{ 1, RISCV_GP_REGNUM, 0 },
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{ 1, RISCV_TP_REGNUM, 0 },
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{ 3, 5, 0 }, /* t0 - t2 */
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{ 4, 28, 0 }, /* t3 - t6 */
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{ 2, RISCV_FP_REGNUM, 0 }, /* s0 - s1 */
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{ 10, 18, 0 }, /* s2 - s11 */
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{ 8, RISCV_A0_REGNUM, 0 }, /* a0 - a7 */
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{ 1, RISCV_PC_REGNUM, 0 },
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{ 1, RISCV_CSR_SSTATUS_REGNUM, 0 },
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{ 0 }
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};
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static const struct regcache_map_entry riscv_fbsd_fpregmap[] =
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{
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{ 32, RISCV_FIRST_FP_REGNUM, 16 },
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{ 1, RISCV_CSR_FCSR_REGNUM, 8 },
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{ 0 }
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};
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/* Register set definitions. */
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const struct regset riscv_fbsd_gregset =
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{
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riscv_fbsd_gregmap, riscv_supply_regset, regcache_collect_regset
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};
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const struct regset riscv_fbsd_fpregset =
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{
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riscv_fbsd_fpregmap, riscv_supply_regset, regcache_collect_regset
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};
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/* Implement the "iterate_over_regset_sections" gdbarch method. */
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static void
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riscv_fbsd_iterate_over_regset_sections (struct gdbarch *gdbarch,
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iterate_over_regset_sections_cb *cb,
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void *cb_data,
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const struct regcache *regcache)
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{
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cb (".reg", RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
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RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch),
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&riscv_fbsd_gregset, NULL, cb_data);
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cb (".reg2", RISCV_FBSD_SIZEOF_FPREGSET, RISCV_FBSD_SIZEOF_FPREGSET,
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&riscv_fbsd_fpregset, NULL, cb_data);
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}
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/* In a signal frame, sp points to a 'struct sigframe' which is
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defined as:
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struct sigframe {
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siginfo_t sf_si;
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ucontext_t sf_uc;
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};
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ucontext_t is defined as:
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struct __ucontext {
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sigset_t uc_sigmask;
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mcontext_t uc_mcontext;
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...
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};
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The mcontext_t contains the general purpose register set followed
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by the floating point register set. The floating point register
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set is only valid if the _MC_FP_VALID flag is set in mc_flags. */
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#define RISCV_SIGFRAME_UCONTEXT_OFFSET 80
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#define RISCV_UCONTEXT_MCONTEXT_OFFSET 16
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#define RISCV_MCONTEXT_FLAG_FP_VALID 0x1
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/* Implement the "init" method of struct tramp_frame. */
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static void
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riscv_fbsd_sigframe_init (const struct tramp_frame *self,
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struct frame_info *this_frame,
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struct trad_frame_cache *this_cache,
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CORE_ADDR func)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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CORE_ADDR sp = get_frame_register_unsigned (this_frame, RISCV_SP_REGNUM);
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CORE_ADDR mcontext_addr
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= (sp
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+ RISCV_SIGFRAME_UCONTEXT_OFFSET
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+ RISCV_UCONTEXT_MCONTEXT_OFFSET);
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gdb_byte buf[4];
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trad_frame_set_reg_regmap (this_cache, riscv_fbsd_gregmap, mcontext_addr,
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RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch));
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CORE_ADDR fpregs_addr
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= mcontext_addr + RISCV_FBSD_NUM_GREGS * riscv_isa_xlen (gdbarch);
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CORE_ADDR fp_flags_addr
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= fpregs_addr + RISCV_FBSD_SIZEOF_FPREGSET;
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if (target_read_memory (fp_flags_addr, buf, 4) == 0
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&& (extract_unsigned_integer (buf, 4, byte_order)
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& RISCV_MCONTEXT_FLAG_FP_VALID))
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trad_frame_set_reg_regmap (this_cache, riscv_fbsd_fpregmap, fpregs_addr,
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RISCV_FBSD_SIZEOF_FPREGSET);
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trad_frame_set_id (this_cache, frame_id_build (sp, func));
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}
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/* RISC-V supports 16-bit instructions ("C") as well as 32-bit
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instructions. The signal trampoline on FreeBSD uses a mix of
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these, but tramp_frame assumes a fixed instruction size. To cope,
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claim that all instructions are 16 bits and use two "slots" for
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32-bit instructions. */
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static const struct tramp_frame riscv_fbsd_sigframe =
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{
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SIGTRAMP_FRAME,
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2,
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{
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{0x850a, ULONGEST_MAX}, /* mov a0, sp */
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{0x0513, ULONGEST_MAX}, /* addi a0, a0, #SF_UC */
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{0x0505, ULONGEST_MAX},
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{0x0293, ULONGEST_MAX}, /* li t0, #SYS_sigreturn */
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{0x1a10, ULONGEST_MAX},
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{0x0073, ULONGEST_MAX}, /* ecall */
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{0x0000, ULONGEST_MAX},
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{TRAMP_SENTINEL_INSN, ULONGEST_MAX}
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},
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riscv_fbsd_sigframe_init
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};
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/* Implement the "get_thread_local_address" gdbarch method. */
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static CORE_ADDR
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riscv_fbsd_get_thread_local_address (struct gdbarch *gdbarch, ptid_t ptid,
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CORE_ADDR lm_addr, CORE_ADDR offset)
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{
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struct regcache *regcache;
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regcache = get_thread_arch_regcache (current_inferior ()->process_target (),
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ptid, gdbarch);
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target_fetch_registers (regcache, RISCV_TP_REGNUM);
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ULONGEST tp;
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if (regcache->cooked_read (RISCV_TP_REGNUM, &tp) != REG_VALID)
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error (_("Unable to fetch %%tp"));
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/* %tp points to the end of the TCB which contains two pointers.
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The first pointer in the TCB points to the DTV array. */
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CORE_ADDR dtv_addr = tp - (gdbarch_ptr_bit (gdbarch) / 8) * 2;
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return fbsd_get_thread_local_address (gdbarch, dtv_addr, lm_addr, offset);
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}
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/* Implement the 'init_osabi' method of struct gdb_osabi_handler. */
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static void
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riscv_fbsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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/* Generic FreeBSD support. */
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fbsd_init_abi (info, gdbarch);
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set_gdbarch_software_single_step (gdbarch, riscv_software_single_step);
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set_solib_svr4_fetch_link_map_offsets (gdbarch,
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(riscv_isa_xlen (gdbarch) == 4
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? svr4_ilp32_fetch_link_map_offsets
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: svr4_lp64_fetch_link_map_offsets));
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tramp_frame_prepend_unwinder (gdbarch, &riscv_fbsd_sigframe);
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set_gdbarch_iterate_over_regset_sections
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(gdbarch, riscv_fbsd_iterate_over_regset_sections);
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set_gdbarch_fetch_tls_load_module_address (gdbarch,
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svr4_fetch_objfile_link_map);
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set_gdbarch_get_thread_local_address (gdbarch,
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riscv_fbsd_get_thread_local_address);
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}
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void _initialize_riscv_fbsd_tdep ();
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void
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_initialize_riscv_fbsd_tdep ()
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{
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gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_FREEBSD,
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riscv_fbsd_init_abi);
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}
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