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10cb538eae
* Makefile.am (CFILES): Add i960c-asm, i960c-dis.c, i960c-opc.c. (ALL_MACHINES): Add i960c-asm.lo, i960c-dis.lo, i960-opc.lo. start-sanitize-cygnus (CLEANFILES): Add stamp-i960. (I960_DEPS): Define. (i960c-opc.h, i960c-opc.c, i960c-asm.c, i960c-dis.c, stamp-i960): New makefile rules. end-sanitize-cygnus (i960-asm.lo, i960c-dis.lo, i960c-opc.lo): New Makefile rules. * Makefile.in: Rebuilt. * configure.in (bfd_i960_arch): Add i960c-opc.lo, i960-asm.o, i960-dis.c to ta. * i960-dis.c (print_insn_i960): Rename to print_insn_i960_orig. * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: New files.
5830 lines
235 KiB
C
5830 lines
235 KiB
C
/* Generic opcode table support for targets using CGEN. -*- C -*-
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CGEN: Cpu tools GENerator
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THIS FILE IS USED TO GENERATE i960c-opc.c.
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Copyright (C) 1998 Free Software Foundation, Inc.
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This file is part of the GNU Binutils and GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "sysdep.h"
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#include <stdio.h>
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#include "ansidecl.h"
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#include "libiberty.h"
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#include "bfd.h"
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#include "symcat.h"
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#include "i960c-opc.h"
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#include "opintl.h"
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/* Used by the ifield rtx function. */
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#define FLD(f) (fields->f)
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/* The hash functions are recorded here to help keep assembler code out of
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the disassembler and vice versa. */
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static int asm_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int asm_hash_insn PARAMS ((const char *));
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static int dis_hash_insn_p PARAMS ((const CGEN_INSN *));
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static unsigned int dis_hash_insn PARAMS ((const char *, CGEN_INSN_INT));
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/* Look up instruction INSN_VALUE and extract its fields.
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INSN, if non-null, is the insn table entry.
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Otherwise INSN_VALUE is examined to compute it.
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LENGTH is the bit length of INSN_VALUE if known, otherwise 0.
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0 is only valid if `insn == NULL && ! CGEN_INT_INSN_P'.
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If INSN != NULL, LENGTH must be valid.
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ALIAS_P is non-zero if alias insns are to be included in the search.
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The result is a pointer to the insn table entry, or NULL if the instruction
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wasn't recognized. */
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const CGEN_INSN *
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i960_cgen_lookup_insn (od, insn, insn_value, length, fields, alias_p)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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CGEN_FIELDS *fields;
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int alias_p;
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{
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unsigned char buf[CGEN_MAX_INSN_SIZE];
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unsigned char *bufp;
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CGEN_INSN_INT base_insn;
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#if CGEN_INT_INSN_P
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CGEN_EXTRACT_INFO *info = NULL;
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#else
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CGEN_EXTRACT_INFO ex_info;
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CGEN_EXTRACT_INFO *info = &ex_info;
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#endif
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#if CGEN_INT_INSN_P
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cgen_put_insn_value (od, buf, length, insn_value);
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bufp = buf;
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base_insn = insn_value; /*???*/
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#else
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ex_info.dis_info = NULL;
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ex_info.insn_bytes = insn_value;
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ex_info.valid = -1;
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base_insn = cgen_get_insn_value (od, buf, length);
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bufp = insn_value;
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#endif
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if (!insn)
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{
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const CGEN_INSN_LIST *insn_list;
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/* The instructions are stored in hash lists.
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Pick the first one and keep trying until we find the right one. */
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insn_list = CGEN_DIS_LOOKUP_INSN (od, bufp, base_insn);
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while (insn_list != NULL)
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{
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insn = insn_list->insn;
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if (alias_p
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|| ! CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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{
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/* Basic bit mask must be correct. */
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/* ??? May wish to allow target to defer this check until the
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extract handler. */
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if ((base_insn & CGEN_INSN_BASE_MASK (insn))
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== CGEN_INSN_BASE_VALUE (insn))
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{
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/* ??? 0 is passed for `pc' */
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int elength = (*CGEN_EXTRACT_FN (insn)) (od, insn, info,
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base_insn, fields,
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(bfd_vma) 0);
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if (elength > 0)
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{
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/* sanity check */
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if (length != 0 && length != elength)
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abort ();
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return insn;
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}
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}
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}
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insn_list = CGEN_DIS_NEXT_INSN (insn_list);
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}
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}
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else
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{
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/* Sanity check: can't pass an alias insn if ! alias_p. */
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if (! alias_p
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&& CGEN_INSN_ATTR (insn, CGEN_INSN_ALIAS))
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abort ();
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/* Sanity check: length must be correct. */
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if (length != CGEN_INSN_BITSIZE (insn))
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abort ();
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/* ??? 0 is passed for `pc' */
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length = (*CGEN_EXTRACT_FN (insn)) (od, insn, info, base_insn, fields,
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(bfd_vma) 0);
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/* Sanity check: must succeed.
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Could relax this later if it ever proves useful. */
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if (length == 0)
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abort ();
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return insn;
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}
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return NULL;
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}
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/* Fill in the operand instances used by INSN whose operands are FIELDS.
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INDICES is a pointer to a buffer of MAX_OPERAND_INSTANCES ints to be filled
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in. */
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void
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i960_cgen_get_insn_operands (od, insn, fields, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN * insn;
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const CGEN_FIELDS * fields;
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int *indices;
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{
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const CGEN_OPERAND_INSTANCE *opinst;
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int i;
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for (i = 0, opinst = CGEN_INSN_OPERANDS (insn);
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opinst != NULL
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&& CGEN_OPERAND_INSTANCE_TYPE (opinst) != CGEN_OPERAND_INSTANCE_END;
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++i, ++opinst)
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{
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const CGEN_OPERAND *op = CGEN_OPERAND_INSTANCE_OPERAND (opinst);
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if (op == NULL)
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indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst);
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else
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indices[i] = i960_cgen_get_int_operand (CGEN_OPERAND_INDEX (op),
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fields);
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}
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}
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/* Cover function to i960_cgen_get_insn_operands when either INSN or FIELDS
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isn't known.
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The INSN, INSN_VALUE, and LENGTH arguments are passed to
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i960_cgen_lookup_insn unchanged.
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The result is the insn table entry or NULL if the instruction wasn't
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recognized. */
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const CGEN_INSN *
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i960_cgen_lookup_get_insn_operands (od, insn, insn_value, length, indices)
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CGEN_OPCODE_DESC od;
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const CGEN_INSN *insn;
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CGEN_INSN_BYTES insn_value;
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int length;
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int *indices;
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{
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CGEN_FIELDS fields;
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/* Pass non-zero for ALIAS_P only if INSN != NULL.
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If INSN == NULL, we want a real insn. */
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insn = i960_cgen_lookup_insn (od, insn, insn_value, length, &fields,
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insn != NULL);
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if (! insn)
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return NULL;
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i960_cgen_get_insn_operands (od, insn, &fields, indices);
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return insn;
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}
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/* Attributes. */
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static const CGEN_ATTR_ENTRY MACH_attr[] =
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{
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{ "base", MACH_BASE },
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{ "i960_ka_sa", MACH_I960_KA_SA },
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{ "i960_ca", MACH_I960_CA },
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{ "max", MACH_MAX },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
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{
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{ "CACHE-ADDR", NULL },
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{ "PC", NULL },
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{ "PROFILE", NULL },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
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{
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{ "ABS-ADDR", NULL },
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{ "NEGATIVE", NULL },
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{ "PCREL-ADDR", NULL },
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{ "RELAX", NULL },
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{ "RELOC", NULL },
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{ "SEM-ONLY", NULL },
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{ "SIGN-OPT", NULL },
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{ "UNSIGNED", NULL },
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{ 0, 0 }
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};
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const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
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{
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{ "ALIAS", NULL },
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{ "COND-CTI", NULL },
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{ "DELAY-SLOT", NULL },
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{ "NO-DIS", NULL },
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{ "RELAX", NULL },
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{ "RELAXABLE", NULL },
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{ "SKIP-CTI", NULL },
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{ "UNCOND-CTI", NULL },
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{ "VIRTUAL", NULL },
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{ 0, 0 }
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};
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CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
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{
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{ "fp", 31 },
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{ "sp", 1 },
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{ "r0", 0 },
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{ "r1", 1 },
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{ "r2", 2 },
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{ "r3", 3 },
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{ "r4", 4 },
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{ "r5", 5 },
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{ "r6", 6 },
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{ "r7", 7 },
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{ "r8", 8 },
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{ "r9", 9 },
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{ "r10", 10 },
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{ "r11", 11 },
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{ "r12", 12 },
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{ "r13", 13 },
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{ "r14", 14 },
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{ "r15", 15 },
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{ "g0", 16 },
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{ "g1", 17 },
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{ "g2", 18 },
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{ "g3", 19 },
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{ "g4", 20 },
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{ "g5", 21 },
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{ "g6", 22 },
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{ "g7", 23 },
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{ "g8", 24 },
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{ "g9", 25 },
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{ "g10", 26 },
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{ "g11", 27 },
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{ "g12", 28 },
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{ "g13", 29 },
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{ "g14", 30 },
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{ "g15", 31 }
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};
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CGEN_KEYWORD i960_cgen_opval_h_gr =
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{
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& i960_cgen_opval_h_gr_entries[0],
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34
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};
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CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
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{
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{ "cc", 0 }
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};
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CGEN_KEYWORD i960_cgen_opval_h_cc =
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{
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& i960_cgen_opval_h_cc_entries[0],
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1
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};
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/* The hardware table. */
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#define HW_ENT(n) i960_cgen_hw_entries[n]
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static const CGEN_HW_ENTRY i960_cgen_hw_entries[] =
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{
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{ HW_H_PC, & HW_ENT (HW_H_PC + 1), "h-pc", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0|(1<<CGEN_HW_PROFILE)|(1<<CGEN_HW_PC), { 0 } } },
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{ HW_H_MEMORY, & HW_ENT (HW_H_MEMORY + 1), "h-memory", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_SINT, & HW_ENT (HW_H_SINT + 1), "h-sint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_UINT, & HW_ENT (HW_H_UINT + 1), "h-uint", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_ADDR, & HW_ENT (HW_H_ADDR + 1), "h-addr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_IADDR, & HW_ENT (HW_H_IADDR + 1), "h-iaddr", CGEN_ASM_KEYWORD, (PTR) 0, { 0, 0, { 0 } } },
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{ HW_H_GR, & HW_ENT (HW_H_GR + 1), "h-gr", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
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{ HW_H_CC, & HW_ENT (HW_H_CC + 1), "h-cc", CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0, 0|(1<<CGEN_HW_CACHE_ADDR)|(1<<CGEN_HW_PROFILE), { 0 } } },
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{ 0 }
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};
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/* The instruction field table. */
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static const CGEN_IFLD i960_cgen_ifld_table[] =
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{
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{ I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, 0, { 0 } } },
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{ I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } },
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{ I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0, 0|(1<<CGEN_IFLD_RELOC)|(1<<CGEN_IFLD_PCREL_ADDR), { 0 } } },
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{ I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, 0|(1<<CGEN_IFLD_UNSIGNED), { 0 } } },
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{ 0 }
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};
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/* The operand table. */
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#define OPERAND(op) CONCAT2 (I960_OPERAND_,op)
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#define OP_ENT(op) i960_cgen_operand_table[OPERAND (op)]
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const CGEN_OPERAND i960_cgen_operand_table[MAX_OPERANDS] =
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{
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/* pc: program counter */
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{ "pc", & HW_ENT (HW_H_PC), 0, 0,
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{ 0, 0|(1<<CGEN_OPERAND_SEM_ONLY), { 0 } } },
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/* src1: source register 1 */
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{ "src1", & HW_ENT (HW_H_GR), 27, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* src2: source register 2 */
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{ "src2", & HW_ENT (HW_H_GR), 13, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* dst: source/dest register */
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{ "dst", & HW_ENT (HW_H_GR), 8, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* lit1: literal 1 */
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{ "lit1", & HW_ENT (HW_H_UINT), 27, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* lit2: literal 2 */
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{ "lit2", & HW_ENT (HW_H_UINT), 13, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* st_src: store src */
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{ "st_src", & HW_ENT (HW_H_GR), 8, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* abase: abase */
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{ "abase", & HW_ENT (HW_H_GR), 13, 5,
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{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
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/* offset: offset */
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{ "offset", & HW_ENT (HW_H_UINT), 20, 12,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* scale: scale */
|
|
{ "scale", & HW_ENT (HW_H_UINT), 22, 3,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* index: index */
|
|
{ "index", & HW_ENT (HW_H_GR), 27, 5,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* optdisp: optional displacement */
|
|
{ "optdisp", & HW_ENT (HW_H_UINT), 0, 32,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* br_src1: branch src1 */
|
|
{ "br_src1", & HW_ENT (HW_H_GR), 8, 5,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* br_src2: branch src2 */
|
|
{ "br_src2", & HW_ENT (HW_H_GR), 13, 5,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* br_disp: branch displacement */
|
|
{ "br_disp", & HW_ENT (HW_H_IADDR), 19, 11,
|
|
{ 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
|
|
/* br_lit1: branch literal 1 */
|
|
{ "br_lit1", & HW_ENT (HW_H_UINT), 8, 5,
|
|
{ 0, 0|(1<<CGEN_OPERAND_UNSIGNED), { 0 } } },
|
|
/* ctrl_disp: ctrl branch disp */
|
|
{ "ctrl_disp", & HW_ENT (HW_H_IADDR), 8, 22,
|
|
{ 0, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), { 0 } } },
|
|
};
|
|
|
|
/* Operand references. */
|
|
|
|
#define INPUT CGEN_OPERAND_INSTANCE_INPUT
|
|
#define OUTPUT CGEN_OPERAND_INSTANCE_OUTPUT
|
|
#define COND_REF CGEN_OPERAND_INSTANCE_COND_REF
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_mulo_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_mulo1_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_mulo2_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_mulo3_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_remo_ops[] = {
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_remo1_ops[] = {
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_remo2_ops[] = {
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_remo3_ops[] = {
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_not_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_not1_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_not2_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_not3_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_emul_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_emul1_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_emul2_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_emul3_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT2), 0, 0 },
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movl_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movl1_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movt_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movt1_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movq_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "f_src1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_src1_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_movq1_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (LIT1), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_modpc_ops[] = {
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_lda_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ld_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldob_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UQI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldos_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_UHI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldib_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldis_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldl_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldt_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ldq_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "h_memory_temp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_temp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_add__VM_index_of_dst_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_st_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stob_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_QI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stos_indirect_index_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_HI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stl_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stt_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_offset", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_offset_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_offset_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_offset_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_optdisp", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_abase", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_abase_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_stq_indirect_index_disp_ops[] = {
|
|
{ INPUT, "f_srcdst", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ INPUT, "st_src", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ST_SRC), 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_add__VM_index_of_st_src_const__WI_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_add__VM_optdisp_add__VM_abase_mul__VM_index_sll__VM_const__WI_1_scale_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpobe_reg_ops[] = {
|
|
{ INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
|
|
{ INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
|
|
{ INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpobe_lit_ops[] = {
|
|
{ INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (BR_LIT1), 0, 0 },
|
|
{ INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
|
|
{ INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpobl_reg_ops[] = {
|
|
{ INPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC1), 0, 0 },
|
|
{ INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
|
|
{ INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpobl_lit_ops[] = {
|
|
{ INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
|
|
{ INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_USI, & OP_ENT (BR_SRC2), 0, 0 },
|
|
{ INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bbc_lit_ops[] = {
|
|
{ INPUT, "br_lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (BR_LIT1), 0, 0 },
|
|
{ INPUT, "br_src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC2), 0, 0 },
|
|
{ INPUT, "br_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (BR_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpi_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpi1_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "src2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC2), 0, 0 },
|
|
{ OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpi2_ops[] = {
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
|
|
{ OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_cmpi3_ops[] = {
|
|
{ INPUT, "lit1", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT1), 0, 0 },
|
|
{ INPUT, "lit2", & HW_ENT (HW_H_UINT), CGEN_MODE_SI, & OP_ENT (LIT2), 0, 0 },
|
|
{ OUTPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_testno_reg_ops[] = {
|
|
{ INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "br_src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (BR_SRC1), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bno_ops[] = {
|
|
{ INPUT, "h_cc_0", & HW_ENT (HW_H_CC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, COND_REF },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, COND_REF },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_b_ops[] = {
|
|
{ INPUT, "ctrl_disp", & HW_ENT (HW_H_IADDR), CGEN_MODE_USI, & OP_ENT (CTRL_DISP), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_offset_ops[] = {
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_index_ops[] = {
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ INPUT, "index", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (INDEX), 0, 0 },
|
|
{ INPUT, "scale", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (SCALE), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bx_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_bx_indirect_disp_ops[] = {
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_callx_disp_ops[] = {
|
|
{ INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ INPUT, "optdisp", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OPTDISP), 0, 0 },
|
|
{ OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_ops[] = {
|
|
{ INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_callx_indirect_offset_ops[] = {
|
|
{ INPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ INPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ INPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ INPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ INPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ INPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ INPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ INPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ INPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ INPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ INPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ INPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ INPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ INPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ INPUT, "offset", & HW_ENT (HW_H_UINT), CGEN_MODE_USI, & OP_ENT (OFFSET), 0, 0 },
|
|
{ INPUT, "abase", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (ABASE), 0, 0 },
|
|
{ OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_ret_ops[] = {
|
|
{ INPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_0", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_4", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_8", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_12", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_16", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_20", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_24", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_28", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_32", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_36", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_40", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_44", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_48", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_52", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_56", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_memory_add__VM_reg__VM_h_gr_31_const__WI_60", & HW_ENT (HW_H_MEMORY), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ OUTPUT, "h_gr_31", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 31, 0 },
|
|
{ OUTPUT, "h_gr_0", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "h_gr_1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 1, 0 },
|
|
{ OUTPUT, "h_gr_2", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 2, 0 },
|
|
{ OUTPUT, "h_gr_3", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 3, 0 },
|
|
{ OUTPUT, "h_gr_4", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 4, 0 },
|
|
{ OUTPUT, "h_gr_5", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 5, 0 },
|
|
{ OUTPUT, "h_gr_6", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 6, 0 },
|
|
{ OUTPUT, "h_gr_7", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 7, 0 },
|
|
{ OUTPUT, "h_gr_8", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 8, 0 },
|
|
{ OUTPUT, "h_gr_9", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 9, 0 },
|
|
{ OUTPUT, "h_gr_10", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 10, 0 },
|
|
{ OUTPUT, "h_gr_11", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 11, 0 },
|
|
{ OUTPUT, "h_gr_12", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 12, 0 },
|
|
{ OUTPUT, "h_gr_13", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 13, 0 },
|
|
{ OUTPUT, "h_gr_14", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 14, 0 },
|
|
{ OUTPUT, "h_gr_15", & HW_ENT (HW_H_GR), CGEN_MODE_SI, 0, 15, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_USI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_calls_ops[] = {
|
|
{ INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ INPUT, "src1", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (SRC1), 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_fmark_ops[] = {
|
|
{ INPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ OUTPUT, "pc", & HW_ENT (HW_H_PC), CGEN_MODE_SI, 0, 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
static const CGEN_OPERAND_INSTANCE fmt_flushreg_ops[] = {
|
|
{ INPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ OUTPUT, "dst", & HW_ENT (HW_H_GR), CGEN_MODE_SI, & OP_ENT (DST), 0, 0 },
|
|
{ 0 }
|
|
};
|
|
|
|
#undef INPUT
|
|
#undef OUTPUT
|
|
#undef COND_REF
|
|
|
|
/* Instruction formats. */
|
|
|
|
#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
|
|
|
|
static const CGEN_IFMT fmt_mulo = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_mulo1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_mulo2 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_mulo3 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_remo = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_remo1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_remo2 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_remo3 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_not = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_not1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_not2 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_not3 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_emul = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_emul1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_emul2 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_emul3 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movl = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movl1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movt = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movt1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movq = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_movq1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_modpc = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_lda_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ld_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldob_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldos_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldib_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldis_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldl_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldt_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ldq_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_st_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stob_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stos_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stl_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stt_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_stq_indirect_index_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpobe_reg = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpobe_lit = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpobl_reg = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpobl_lit = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bbc_lit = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpi = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpi1 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpi2 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_cmpi3 = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_testno_reg = {
|
|
32, 32, 0xff002003, { F (F_OPCODE), F (F_BR_SRC1), F (F_BR_SRC2), F (F_BR_M1), F (F_BR_DISP), F (F_BR_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bno = {
|
|
32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_b = {
|
|
32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bx_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bx_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bx_indirect_index = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bx_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_bx_indirect_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_callx_disp = {
|
|
32, 64, 0xff003c60, { F (F_OPCODE), F (F_OPTDISP), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_callx_indirect = {
|
|
32, 32, 0xff003c60, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEB), F (F_SCALE), F (F_ZEROB), F (F_INDEX), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_callx_indirect_offset = {
|
|
32, 32, 0xff003000, { F (F_OPCODE), F (F_SRCDST), F (F_ABASE), F (F_MODEA), F (F_ZEROA), F (F_OFFSET), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_ret = {
|
|
32, 32, 0xff000003, { F (F_OPCODE), F (F_CTRL_DISP), F (F_CTRL_ZERO), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_calls = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_fmark = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
static const CGEN_IFMT fmt_flushreg = {
|
|
32, 32, 0xff003fe0, { F (F_OPCODE), F (F_SRCDST), F (F_SRC2), F (F_M3), F (F_M2), F (F_M1), F (F_OPCODE2), F (F_ZERO), F (F_SRC1), 0 }
|
|
};
|
|
|
|
#undef F
|
|
|
|
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
|
|
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
|
|
/* The instruction table.
|
|
This is currently non-static because the simulator accesses it
|
|
directly. */
|
|
|
|
const CGEN_INSN i960_cgen_insn_table_entries[MAX_INSNS] =
|
|
{
|
|
/* Special null first entry.
|
|
A `num' value of zero is thus invalid.
|
|
Also, the special `invalid' insn resides here. */
|
|
{ { 0 }, 0 },
|
|
/* mulo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MULO, "mulo", "mulo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x70000080 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* mulo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MULO1, "mulo1", "mulo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x70000880 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* mulo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MULO2, "mulo2", "mulo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x70001080 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* mulo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MULO3, "mulo3", "mulo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x70001880 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMO, "remo", "remo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x70000400 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMO1, "remo1", "remo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x70000c00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMO2, "remo2", "remo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x70001400 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMO3, "remo3", "remo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x70001c00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVO, "divo", "divo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x70000580 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVO1, "divo1", "divo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x70000d80 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVO2, "divo2", "divo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x70001580 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVO3, "divo3", "divo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x70001d80 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remi $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMI, "remi", "remi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x74000400 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remi $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMI1, "remi1", "remi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x74000c00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remi $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMI2, "remi2", "remi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x74001400 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* remi $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_REMI3, "remi3", "remi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x74001c00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divi $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVI, "divi", "divi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x74000580 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divi $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVI1, "divi1", "divi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x74000d80 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divi $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVI2, "divi2", "divi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x74001580 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* divi $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_DIVI3, "divi3", "divi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x74001d80 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* addo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ADDO, "addo", "addo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x59000000 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* addo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ADDO1, "addo1", "addo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x59000800 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* addo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ADDO2, "addo2", "addo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x59001000 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* addo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ADDO3, "addo3", "addo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x59001800 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* subo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SUBO, "subo", "subo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x59000100 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* subo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SUBO1, "subo1", "subo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x59000900 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* subo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SUBO2, "subo2", "subo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x59001100 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* subo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SUBO3, "subo3", "subo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x59001900 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notbit $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTBIT, "notbit", "notbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000000 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notbit $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTBIT1, "notbit1", "notbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000800 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notbit $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTBIT2, "notbit2", "notbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001000 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notbit $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTBIT3, "notbit3", "notbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001800 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* and $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_AND, "and", "and",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000080 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* and $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_AND1, "and1", "and",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000880 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* and $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_AND2, "and2", "and",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001080 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* and $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_AND3, "and3", "and",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001880 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* andnot $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ANDNOT, "andnot", "andnot",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x58000100 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* andnot $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ANDNOT1, "andnot1", "andnot",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x58000900 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* andnot $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ANDNOT2, "andnot2", "andnot",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x58001100 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* andnot $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ANDNOT3, "andnot3", "andnot",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x58001900 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* setbit $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SETBIT, "setbit", "setbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000180 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* setbit $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SETBIT1, "setbit1", "setbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000980 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* setbit $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SETBIT2, "setbit2", "setbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001180 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* setbit $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SETBIT3, "setbit3", "setbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001980 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notand $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTAND, "notand", "notand",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x58000200 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notand $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTAND1, "notand1", "notand",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x58000a00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notand $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTAND2, "notand2", "notand",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x58001200 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* notand $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOTAND3, "notand3", "notand",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x58001a00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* xor $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_XOR, "xor", "xor",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000300 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* xor $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_XOR1, "xor1", "xor",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000b00 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* xor $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_XOR2, "xor2", "xor",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001300 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* xor $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_XOR3, "xor3", "xor",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001b00 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* or $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_OR, "or", "or",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000380 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* or $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_OR1, "or1", "or",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000b80 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* or $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_OR2, "or2", "or",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001380 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* or $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_OR3, "or3", "or",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001b80 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* nor $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOR, "nor", "nor",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x58000400 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* nor $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOR1, "nor1", "nor",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x58000c00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* nor $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOR2, "nor2", "nor",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x58001400 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* nor $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOR3, "nor3", "nor",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x58001c00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* not $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOT, "not", "not",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not, { 0x58000500 },
|
|
(PTR) & fmt_not_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* not $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOT1, "not1", "not",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not1, { 0x58000d00 },
|
|
(PTR) & fmt_not1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* not $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOT2, "not2", "not",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not2, { 0x58001500 },
|
|
(PTR) & fmt_not2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* not $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_NOT3, "not3", "not",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not3, { 0x58001d00 },
|
|
(PTR) & fmt_not3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* clrbit $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CLRBIT, "clrbit", "clrbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo, { 0x58000600 },
|
|
(PTR) & fmt_mulo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* clrbit $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CLRBIT1, "clrbit1", "clrbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo1, { 0x58000e00 },
|
|
(PTR) & fmt_mulo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* clrbit $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CLRBIT2, "clrbit2", "clrbit",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo2, { 0x58001600 },
|
|
(PTR) & fmt_mulo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* clrbit $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CLRBIT3, "clrbit3", "clrbit",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_mulo3, { 0x58001e00 },
|
|
(PTR) & fmt_mulo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shlo $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLO, "shlo", "shlo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x59000600 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shlo $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLO1, "shlo1", "shlo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x59000e00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shlo $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLO2, "shlo2", "shlo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x59001600 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shlo $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLO3, "shlo3", "shlo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x59001e00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shro $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRO, "shro", "shro",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x59000400 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shro $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRO1, "shro1", "shro",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x59000c00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shro $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRO2, "shro2", "shro",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x59001400 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shro $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRO3, "shro3", "shro",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x59001c00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shli $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLI, "shli", "shli",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x59000700 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shli $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLI1, "shli1", "shli",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x59000f00 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shli $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLI2, "shli2", "shli",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x59001700 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shli $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHLI3, "shli3", "shli",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x59001f00 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shri $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRI, "shri", "shri",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo, { 0x59000580 },
|
|
(PTR) & fmt_remo_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shri $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRI1, "shri1", "shri",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo1, { 0x59000d80 },
|
|
(PTR) & fmt_remo1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shri $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRI2, "shri2", "shri",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo2, { 0x59001580 },
|
|
(PTR) & fmt_remo2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* shri $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_SHRI3, "shri3", "shri",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_remo3, { 0x59001d80 },
|
|
(PTR) & fmt_remo3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* emul $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_EMUL, "emul", "emul",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_emul, { 0x67000000 },
|
|
(PTR) & fmt_emul_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* emul $lit1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_EMUL1, "emul1", "emul",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_emul1, { 0x67000800 },
|
|
(PTR) & fmt_emul1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* emul $src1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_EMUL2, "emul2", "emul",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_emul2, { 0x67001000 },
|
|
(PTR) & fmt_emul2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* emul $lit1, $lit2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_EMUL3, "emul3", "emul",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_emul3, { 0x67001800 },
|
|
(PTR) & fmt_emul3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* mov $src1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOV, "mov", "mov",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not2, { 0x5c001600 },
|
|
(PTR) & fmt_not2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* mov $lit1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOV1, "mov1", "mov",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_not3, { 0x5c001e00 },
|
|
(PTR) & fmt_not3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movl $src1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVL, "movl", "movl",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movl, { 0x5d001600 },
|
|
(PTR) & fmt_movl_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movl $lit1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVL1, "movl1", "movl",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movl1, { 0x5d001e00 },
|
|
(PTR) & fmt_movl1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movt $src1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVT, "movt", "movt",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movt, { 0x5e001600 },
|
|
(PTR) & fmt_movt_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movt $lit1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVT1, "movt1", "movt",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movt1, { 0x5e001e00 },
|
|
(PTR) & fmt_movt1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movq $src1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVQ, "movq", "movq",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movq, { 0x5f001600 },
|
|
(PTR) & fmt_movq_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* movq $lit1, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MOVQ1, "movq1", "movq",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (DST), 0 } },
|
|
& fmt_movq1, { 0x5f001e00 },
|
|
(PTR) & fmt_movq1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* modpc $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MODPC, "modpc", "modpc",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_modpc, { 0x65000280 },
|
|
(PTR) & fmt_modpc_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* modac $src1, $src2, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_MODAC, "modac", "modac",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), ',', ' ', OP (DST), 0 } },
|
|
& fmt_modpc, { 0x64000280 },
|
|
(PTR) & fmt_modpc_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_OFFSET, "lda-offset", "lda",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_offset, { 0x8c000000 },
|
|
(PTR) & fmt_lda_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_indirect_offset, { 0x8c002000 },
|
|
(PTR) & fmt_lda_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDIRECT, "lda-indirect", "lda",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_indirect, { 0x8c001000 },
|
|
(PTR) & fmt_lda_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_indirect_index, { 0x8c001c00 },
|
|
(PTR) & fmt_lda_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_DISP, "lda-disp", "lda",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_disp, { 0x8c003000 },
|
|
(PTR) & fmt_lda_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_indirect_disp, { 0x8c003400 },
|
|
(PTR) & fmt_lda_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_index_disp, { 0x8c003800 },
|
|
(PTR) & fmt_lda_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* lda $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_lda_indirect_index_disp, { 0x8c003c00 },
|
|
(PTR) & fmt_lda_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_OFFSET, "ld-offset", "ld",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_offset, { 0x90000000 },
|
|
(PTR) & fmt_ld_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_indirect_offset, { 0x90002000 },
|
|
(PTR) & fmt_ld_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDIRECT, "ld-indirect", "ld",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_indirect, { 0x90001000 },
|
|
(PTR) & fmt_ld_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_indirect_index, { 0x90001c00 },
|
|
(PTR) & fmt_ld_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_DISP, "ld-disp", "ld",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_disp, { 0x90003000 },
|
|
(PTR) & fmt_ld_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_indirect_disp, { 0x90003400 },
|
|
(PTR) & fmt_ld_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_index_disp, { 0x90003800 },
|
|
(PTR) & fmt_ld_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ld $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ld_indirect_index_disp, { 0x90003c00 },
|
|
(PTR) & fmt_ld_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_offset, { 0x80000000 },
|
|
(PTR) & fmt_ldob_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_indirect_offset, { 0x80002000 },
|
|
(PTR) & fmt_ldob_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_indirect, { 0x80001000 },
|
|
(PTR) & fmt_ldob_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_indirect_index, { 0x80001c00 },
|
|
(PTR) & fmt_ldob_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_DISP, "ldob-disp", "ldob",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_disp, { 0x80003000 },
|
|
(PTR) & fmt_ldob_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_indirect_disp, { 0x80003400 },
|
|
(PTR) & fmt_ldob_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_index_disp, { 0x80003800 },
|
|
(PTR) & fmt_ldob_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldob $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldob_indirect_index_disp, { 0x80003c00 },
|
|
(PTR) & fmt_ldob_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_offset, { 0x88000000 },
|
|
(PTR) & fmt_ldos_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_indirect_offset, { 0x88002000 },
|
|
(PTR) & fmt_ldos_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_indirect, { 0x88001000 },
|
|
(PTR) & fmt_ldos_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_indirect_index, { 0x88001c00 },
|
|
(PTR) & fmt_ldos_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_DISP, "ldos-disp", "ldos",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_disp, { 0x88003000 },
|
|
(PTR) & fmt_ldos_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_indirect_disp, { 0x88003400 },
|
|
(PTR) & fmt_ldos_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_index_disp, { 0x88003800 },
|
|
(PTR) & fmt_ldos_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldos $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldos_indirect_index_disp, { 0x88003c00 },
|
|
(PTR) & fmt_ldos_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_offset, { 0xc0000000 },
|
|
(PTR) & fmt_ldib_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_indirect_offset, { 0xc0002000 },
|
|
(PTR) & fmt_ldib_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_indirect, { 0xc0001000 },
|
|
(PTR) & fmt_ldib_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_indirect_index, { 0xc0001c00 },
|
|
(PTR) & fmt_ldib_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_DISP, "ldib-disp", "ldib",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_disp, { 0xc0003000 },
|
|
(PTR) & fmt_ldib_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_indirect_disp, { 0xc0003400 },
|
|
(PTR) & fmt_ldib_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_index_disp, { 0xc0003800 },
|
|
(PTR) & fmt_ldib_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldib $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldib_indirect_index_disp, { 0xc0003c00 },
|
|
(PTR) & fmt_ldib_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_offset, { 0xc8000000 },
|
|
(PTR) & fmt_ldis_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_indirect_offset, { 0xc8002000 },
|
|
(PTR) & fmt_ldis_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_indirect, { 0xc8001000 },
|
|
(PTR) & fmt_ldis_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_indirect_index, { 0xc8001c00 },
|
|
(PTR) & fmt_ldis_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_DISP, "ldis-disp", "ldis",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_disp, { 0xc8003000 },
|
|
(PTR) & fmt_ldis_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_indirect_disp, { 0xc8003400 },
|
|
(PTR) & fmt_ldis_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_index_disp, { 0xc8003800 },
|
|
(PTR) & fmt_ldis_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldis $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldis_indirect_index_disp, { 0xc8003c00 },
|
|
(PTR) & fmt_ldis_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_OFFSET, "ldl-offset", "ldl",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_offset, { 0x98000000 },
|
|
(PTR) & fmt_ldl_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_indirect_offset, { 0x98002000 },
|
|
(PTR) & fmt_ldl_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_indirect, { 0x98001000 },
|
|
(PTR) & fmt_ldl_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_indirect_index, { 0x98001c00 },
|
|
(PTR) & fmt_ldl_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_DISP, "ldl-disp", "ldl",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_disp, { 0x98003000 },
|
|
(PTR) & fmt_ldl_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_indirect_disp, { 0x98003400 },
|
|
(PTR) & fmt_ldl_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_index_disp, { 0x98003800 },
|
|
(PTR) & fmt_ldl_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldl $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldl_indirect_index_disp, { 0x98003c00 },
|
|
(PTR) & fmt_ldl_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_OFFSET, "ldt-offset", "ldt",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_offset, { 0xa0000000 },
|
|
(PTR) & fmt_ldt_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_indirect_offset, { 0xa0002000 },
|
|
(PTR) & fmt_ldt_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_indirect, { 0xa0001000 },
|
|
(PTR) & fmt_ldt_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_indirect_index, { 0xa0001c00 },
|
|
(PTR) & fmt_ldt_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_DISP, "ldt-disp", "ldt",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_disp, { 0xa0003000 },
|
|
(PTR) & fmt_ldt_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_indirect_disp, { 0xa0003400 },
|
|
(PTR) & fmt_ldt_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_index_disp, { 0xa0003800 },
|
|
(PTR) & fmt_ldt_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldt $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldt_indirect_index_disp, { 0xa0003c00 },
|
|
(PTR) & fmt_ldt_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $offset, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq",
|
|
{ { MNEM, ' ', OP (OFFSET), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_offset, { 0xb0000000 },
|
|
(PTR) & fmt_ldq_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $offset($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_indirect_offset, { 0xb0002000 },
|
|
(PTR) & fmt_ldq_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq ($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_indirect, { 0xb0001000 },
|
|
(PTR) & fmt_ldq_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq ($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_indirect_index, { 0xb0001c00 },
|
|
(PTR) & fmt_ldq_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $optdisp, $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_DISP, "ldq-disp", "ldq",
|
|
{ { MNEM, ' ', OP (OPTDISP), ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_disp, { 0xb0003000 },
|
|
(PTR) & fmt_ldq_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $optdisp($abase), $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_indirect_disp, { 0xb0003400 },
|
|
(PTR) & fmt_ldq_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $optdisp[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq",
|
|
{ { MNEM, ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_index_disp, { 0xb0003800 },
|
|
(PTR) & fmt_ldq_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* ldq $optdisp($abase)[$index*S$scale], $dst */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', ',', ' ', OP (DST), 0 } },
|
|
& fmt_ldq_indirect_index_disp, { 0xb0003c00 },
|
|
(PTR) & fmt_ldq_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_OFFSET, "st-offset", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_st_offset, { 0x92000000 },
|
|
(PTR) & fmt_st_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_st_indirect_offset, { 0x92002000 },
|
|
(PTR) & fmt_st_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDIRECT, "st-indirect", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_st_indirect, { 0x92001000 },
|
|
(PTR) & fmt_st_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_st_indirect_index, { 0x92001c00 },
|
|
(PTR) & fmt_st_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_DISP, "st-disp", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_st_disp, { 0x92003000 },
|
|
(PTR) & fmt_st_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_st_indirect_disp, { 0x92003400 },
|
|
(PTR) & fmt_st_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDEX_DISP, "st-index-disp", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_st_index_disp, { 0x92003800 },
|
|
(PTR) & fmt_st_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* st $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_st_indirect_index_disp, { 0x92003c00 },
|
|
(PTR) & fmt_st_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_OFFSET, "stob-offset", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_stob_offset, { 0x82000000 },
|
|
(PTR) & fmt_stob_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stob_indirect_offset, { 0x82002000 },
|
|
(PTR) & fmt_stob_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDIRECT, "stob-indirect", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stob_indirect, { 0x82001000 },
|
|
(PTR) & fmt_stob_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stob_indirect_index, { 0x82001c00 },
|
|
(PTR) & fmt_stob_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_DISP, "stob-disp", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_stob_disp, { 0x82003000 },
|
|
(PTR) & fmt_stob_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stob_indirect_disp, { 0x82003400 },
|
|
(PTR) & fmt_stob_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_stob_index_disp, { 0x82003800 },
|
|
(PTR) & fmt_stob_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stob $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stob_indirect_index_disp, { 0x82003c00 },
|
|
(PTR) & fmt_stob_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_OFFSET, "stos-offset", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_stos_offset, { 0x8a000000 },
|
|
(PTR) & fmt_stos_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stos_indirect_offset, { 0x8a002000 },
|
|
(PTR) & fmt_stos_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDIRECT, "stos-indirect", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stos_indirect, { 0x8a001000 },
|
|
(PTR) & fmt_stos_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stos_indirect_index, { 0x8a001c00 },
|
|
(PTR) & fmt_stos_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_DISP, "stos-disp", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_stos_disp, { 0x8a003000 },
|
|
(PTR) & fmt_stos_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stos_indirect_disp, { 0x8a003400 },
|
|
(PTR) & fmt_stos_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_stos_index_disp, { 0x8a003800 },
|
|
(PTR) & fmt_stos_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stos $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stos_indirect_index_disp, { 0x8a003c00 },
|
|
(PTR) & fmt_stos_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_OFFSET, "stl-offset", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_stl_offset, { 0x9a000000 },
|
|
(PTR) & fmt_stl_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stl_indirect_offset, { 0x9a002000 },
|
|
(PTR) & fmt_stl_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDIRECT, "stl-indirect", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stl_indirect, { 0x9a001000 },
|
|
(PTR) & fmt_stl_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stl_indirect_index, { 0x9a001c00 },
|
|
(PTR) & fmt_stl_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_DISP, "stl-disp", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_stl_disp, { 0x9a003000 },
|
|
(PTR) & fmt_stl_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stl_indirect_disp, { 0x9a003400 },
|
|
(PTR) & fmt_stl_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_stl_index_disp, { 0x9a003800 },
|
|
(PTR) & fmt_stl_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stl $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stl_indirect_index_disp, { 0x9a003c00 },
|
|
(PTR) & fmt_stl_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_OFFSET, "stt-offset", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_stt_offset, { 0xa2000000 },
|
|
(PTR) & fmt_stt_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stt_indirect_offset, { 0xa2002000 },
|
|
(PTR) & fmt_stt_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDIRECT, "stt-indirect", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stt_indirect, { 0xa2001000 },
|
|
(PTR) & fmt_stt_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stt_indirect_index, { 0xa2001c00 },
|
|
(PTR) & fmt_stt_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_DISP, "stt-disp", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_stt_disp, { 0xa2003000 },
|
|
(PTR) & fmt_stt_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stt_indirect_disp, { 0xa2003400 },
|
|
(PTR) & fmt_stt_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_stt_index_disp, { 0xa2003800 },
|
|
(PTR) & fmt_stt_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stt $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stt_indirect_index_disp, { 0xa2003c00 },
|
|
(PTR) & fmt_stt_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $offset */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_OFFSET, "stq-offset", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), 0 } },
|
|
& fmt_stq_offset, { 0xb2000000 },
|
|
(PTR) & fmt_stq_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stq_indirect_offset, { 0xb2002000 },
|
|
(PTR) & fmt_stq_indirect_offset_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDIRECT, "stq-indirect", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stq_indirect, { 0xb2001000 },
|
|
(PTR) & fmt_stq_indirect_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stq_indirect_index, { 0xb2001c00 },
|
|
(PTR) & fmt_stq_indirect_index_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_DISP, "stq-disp", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), 0 } },
|
|
& fmt_stq_disp, { 0xb2003000 },
|
|
(PTR) & fmt_stq_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_stq_indirect_disp, { 0xb2003400 },
|
|
(PTR) & fmt_stq_indirect_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $optdisp[$index*S$scale */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '[', OP (INDEX), '*', 'S', OP (SCALE), 0 } },
|
|
& fmt_stq_index_disp, { 0xb2003800 },
|
|
(PTR) & fmt_stq_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* stq $st_src, $optdisp($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq",
|
|
{ { MNEM, ' ', OP (ST_SRC), ',', ' ', OP (OPTDISP), '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_stq_indirect_index_disp, { 0xb2003c00 },
|
|
(PTR) & fmt_stq_indirect_index_disp_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpobe $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x32000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobe $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x32002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobne $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x35000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobne $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x35002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobl $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_reg, { 0x34000000 },
|
|
(PTR) & fmt_cmpobl_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobl $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_lit, { 0x34002000 },
|
|
(PTR) & fmt_cmpobl_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpoble $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_reg, { 0x36000000 },
|
|
(PTR) & fmt_cmpobl_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpoble $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_lit, { 0x36002000 },
|
|
(PTR) & fmt_cmpobl_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobg $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_reg, { 0x31000000 },
|
|
(PTR) & fmt_cmpobl_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobg $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_lit, { 0x31002000 },
|
|
(PTR) & fmt_cmpobl_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobge $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_reg, { 0x33000000 },
|
|
(PTR) & fmt_cmpobl_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpobge $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobl_lit, { 0x33002000 },
|
|
(PTR) & fmt_cmpobl_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibe $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x3a000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibe $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x3a002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibne $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x3d000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibne $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x3d002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibl $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x3c000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibl $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x3c002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpible $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x3e000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpible $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x3e002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibg $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x39000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibg $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x39002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibge $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x3b000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpibge $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_lit, { 0x3b002000 },
|
|
(PTR) & fmt_cmpobe_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bbc $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BBC_REG, "bbc-reg", "bbc",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x30000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bbc $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BBC_LIT, "bbc-lit", "bbc",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_bbc_lit, { 0x30002000 },
|
|
(PTR) & fmt_bbc_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bbs $br_src1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BBS_REG, "bbs-reg", "bbs",
|
|
{ { MNEM, ' ', OP (BR_SRC1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_cmpobe_reg, { 0x37000000 },
|
|
(PTR) & fmt_cmpobe_reg_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bbs $br_lit1, $br_src2, $br_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BBS_LIT, "bbs-lit", "bbs",
|
|
{ { MNEM, ' ', OP (BR_LIT1), ',', ' ', OP (BR_SRC2), ',', ' ', OP (BR_DISP), 0 } },
|
|
& fmt_bbc_lit, { 0x37002000 },
|
|
(PTR) & fmt_bbc_lit_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* cmpi $src1, $src2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPI, "cmpi", "cmpi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
|
|
& fmt_cmpi, { 0x5a002080 },
|
|
(PTR) & fmt_cmpi_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpi $lit1, $src2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPI1, "cmpi1", "cmpi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
|
|
& fmt_cmpi1, { 0x5a002880 },
|
|
(PTR) & fmt_cmpi1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpi $src1, $lit2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPI2, "cmpi2", "cmpi",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
|
|
& fmt_cmpi2, { 0x5a003080 },
|
|
(PTR) & fmt_cmpi2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpi $lit1, $lit2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPI3, "cmpi3", "cmpi",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
|
|
& fmt_cmpi3, { 0x5a003880 },
|
|
(PTR) & fmt_cmpi3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpo $src1, $src2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPO, "cmpo", "cmpo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (SRC2), 0 } },
|
|
& fmt_cmpi, { 0x5a002000 },
|
|
(PTR) & fmt_cmpi_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpo $lit1, $src2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPO1, "cmpo1", "cmpo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (SRC2), 0 } },
|
|
& fmt_cmpi1, { 0x5a002800 },
|
|
(PTR) & fmt_cmpi1_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpo $src1, $lit2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPO2, "cmpo2", "cmpo",
|
|
{ { MNEM, ' ', OP (SRC1), ',', ' ', OP (LIT2), 0 } },
|
|
& fmt_cmpi2, { 0x5a003000 },
|
|
(PTR) & fmt_cmpi2_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* cmpo $lit1, $lit2 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CMPO3, "cmpo3", "cmpo",
|
|
{ { MNEM, ' ', OP (LIT1), ',', ' ', OP (LIT2), 0 } },
|
|
& fmt_cmpi3, { 0x5a003800 },
|
|
(PTR) & fmt_cmpi3_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testno $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTNO_REG, "testno-reg", "testno",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x20000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testg $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTG_REG, "testg-reg", "testg",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x21000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* teste $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTE_REG, "teste-reg", "teste",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x22000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testge $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTGE_REG, "testge-reg", "testge",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x23000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testl $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTL_REG, "testl-reg", "testl",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x24000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testne $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTNE_REG, "testne-reg", "testne",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x25000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testle $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTLE_REG, "testle-reg", "testle",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x26000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* testo $br_src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_TESTO_REG, "testo-reg", "testo",
|
|
{ { MNEM, ' ', OP (BR_SRC1), 0 } },
|
|
& fmt_testno_reg, { 0x27000000 },
|
|
(PTR) & fmt_testno_reg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
/* bno $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BNO, "bno", "bno",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x10000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bg $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BG, "bg", "bg",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x11000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* be $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BE, "be", "be",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x12000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bge $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BGE, "bge", "bge",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x13000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bl $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BL, "bl", "bl",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x14000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bne $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BNE, "bne", "bne",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x15000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* ble $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BLE, "ble", "ble",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x16000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* bo $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BO, "bo", "bo",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_bno, { 0x17000000 },
|
|
(PTR) & fmt_bno_ops[0],
|
|
{ 0, 0|A(COND_CTI)|A(COND_CTI), { 0 } }
|
|
},
|
|
/* b $ctrl_disp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_B, "b", "b",
|
|
{ { MNEM, ' ', OP (CTRL_DISP), 0 } },
|
|
& fmt_b, { 0x8000000 },
|
|
(PTR) & fmt_b_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* bx $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_bx_indirect_offset, { 0x84002000 },
|
|
(PTR) & fmt_bx_indirect_offset_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* bx ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BX_INDIRECT, "bx-indirect", "bx",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_bx_indirect, { 0x84001000 },
|
|
(PTR) & fmt_bx_indirect_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* bx ($abase)[$index*S$scale] */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', '[', OP (INDEX), '*', 'S', OP (SCALE), ']', 0 } },
|
|
& fmt_bx_indirect_index, { 0x84001c00 },
|
|
(PTR) & fmt_bx_indirect_index_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* bx $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BX_DISP, "bx-disp", "bx",
|
|
{ { MNEM, ' ', OP (OPTDISP), 0 } },
|
|
& fmt_bx_disp, { 0x84003000 },
|
|
(PTR) & fmt_bx_disp_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* bx $optdisp($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx",
|
|
{ { MNEM, ' ', OP (OPTDISP), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_bx_indirect_disp, { 0x84003400 },
|
|
(PTR) & fmt_bx_indirect_disp_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* callx $optdisp */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CALLX_DISP, "callx-disp", "callx",
|
|
{ { MNEM, ' ', OP (OPTDISP), 0 } },
|
|
& fmt_callx_disp, { 0x86003000 },
|
|
(PTR) & fmt_callx_disp_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* callx ($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx",
|
|
{ { MNEM, ' ', '(', OP (ABASE), ')', 0 } },
|
|
& fmt_callx_indirect, { 0x86001000 },
|
|
(PTR) & fmt_callx_indirect_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* callx $offset($abase) */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx",
|
|
{ { MNEM, ' ', OP (OFFSET), '(', OP (ABASE), ')', 0 } },
|
|
& fmt_callx_indirect_offset, { 0x86002000 },
|
|
(PTR) & fmt_callx_indirect_offset_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* ret */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_RET, "ret", "ret",
|
|
{ { MNEM, 0 } },
|
|
& fmt_ret, { 0xa000000 },
|
|
(PTR) & fmt_ret_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* calls $src1 */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_CALLS, "calls", "calls",
|
|
{ { MNEM, ' ', OP (SRC1), 0 } },
|
|
& fmt_calls, { 0x66003000 },
|
|
(PTR) & fmt_calls_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* fmark */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_FMARK, "fmark", "fmark",
|
|
{ { MNEM, 0 } },
|
|
& fmt_fmark, { 0x66003e00 },
|
|
(PTR) & fmt_fmark_ops[0],
|
|
{ 0, 0|A(UNCOND_CTI)|A(UNCOND_CTI), { 0 } }
|
|
},
|
|
/* flushreg */
|
|
{
|
|
{ 1, 1, 1, 1 },
|
|
I960_INSN_FLUSHREG, "flushreg", "flushreg",
|
|
{ { MNEM, 0 } },
|
|
& fmt_flushreg, { 0x66003e80 },
|
|
(PTR) & fmt_flushreg_ops[0],
|
|
{ 0, 0, { 0 } }
|
|
},
|
|
};
|
|
|
|
#undef A
|
|
#undef MNEM
|
|
#undef OP
|
|
|
|
static const CGEN_INSN_TABLE insn_table =
|
|
{
|
|
& i960_cgen_insn_table_entries[0],
|
|
sizeof (CGEN_INSN),
|
|
MAX_INSNS,
|
|
NULL
|
|
};
|
|
|
|
/* Formats for ALIAS macro-insns. */
|
|
|
|
#define F(f) & i960_cgen_ifld_table[CONCAT2 (I960_,f)]
|
|
|
|
#undef F
|
|
|
|
/* Each non-simple macro entry points to an array of expansion possibilities. */
|
|
|
|
#define A(a) (1 << CONCAT2 (CGEN_INSN_,a))
|
|
#define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
|
|
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
|
|
|
|
/* The macro instruction table. */
|
|
|
|
static const CGEN_INSN macro_insn_table_entries[] =
|
|
{
|
|
};
|
|
|
|
#undef A
|
|
#undef MNEM
|
|
#undef OP
|
|
|
|
static const CGEN_INSN_TABLE macro_insn_table =
|
|
{
|
|
& macro_insn_table_entries[0],
|
|
sizeof (CGEN_INSN),
|
|
(sizeof (macro_insn_table_entries) /
|
|
sizeof (macro_insn_table_entries[0])),
|
|
NULL
|
|
};
|
|
|
|
static void
|
|
init_tables ()
|
|
{
|
|
}
|
|
|
|
/* Return non-zero if INSN is to be added to the hash table.
|
|
Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
|
|
|
|
static int
|
|
asm_hash_insn_p (insn)
|
|
const CGEN_INSN * insn;
|
|
{
|
|
return CGEN_ASM_HASH_P (insn);
|
|
}
|
|
|
|
static int
|
|
dis_hash_insn_p (insn)
|
|
const CGEN_INSN * insn;
|
|
{
|
|
/* If building the hash table and the NO-DIS attribute is present,
|
|
ignore. */
|
|
if (CGEN_INSN_ATTR (insn, CGEN_INSN_NO_DIS))
|
|
return 0;
|
|
return CGEN_DIS_HASH_P (insn);
|
|
}
|
|
|
|
/* The result is the hash value of the insn.
|
|
Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
|
|
|
|
static unsigned int
|
|
asm_hash_insn (mnem)
|
|
const char * mnem;
|
|
{
|
|
return CGEN_ASM_HASH (mnem);
|
|
}
|
|
|
|
/* BUF is a pointer to the insn's bytes in target order.
|
|
VALUE is an integer of the first CGEN_BASE_INSN_BITSIZE bits,
|
|
host order. */
|
|
|
|
static unsigned int
|
|
dis_hash_insn (buf, value)
|
|
const char * buf;
|
|
CGEN_INSN_INT value;
|
|
{
|
|
return CGEN_DIS_HASH (buf, value);
|
|
}
|
|
|
|
/* Initialize an opcode table and return a descriptor.
|
|
It's much like opening a file, and must be the first function called. */
|
|
|
|
CGEN_OPCODE_DESC
|
|
i960_cgen_opcode_open (mach, endian)
|
|
int mach;
|
|
enum cgen_endian endian;
|
|
{
|
|
CGEN_OPCODE_TABLE * table = (CGEN_OPCODE_TABLE *) xmalloc (sizeof (CGEN_OPCODE_TABLE));
|
|
static int init_p;
|
|
|
|
if (! init_p)
|
|
{
|
|
init_tables ();
|
|
init_p = 1;
|
|
}
|
|
|
|
memset (table, 0, sizeof (*table));
|
|
|
|
CGEN_OPCODE_MACH (table) = mach;
|
|
CGEN_OPCODE_ENDIAN (table) = endian;
|
|
/* FIXME: for the sparc case we can determine insn-endianness statically.
|
|
The worry here is where both data and insn endian can be independently
|
|
chosen, in which case this function will need another argument.
|
|
Actually, will want to allow for more arguments in the future anyway. */
|
|
CGEN_OPCODE_INSN_ENDIAN (table) = endian;
|
|
|
|
CGEN_OPCODE_HW_LIST (table) = & i960_cgen_hw_entries[0];
|
|
|
|
CGEN_OPCODE_IFLD_TABLE (table) = & i960_cgen_ifld_table[0];
|
|
|
|
CGEN_OPCODE_OPERAND_TABLE (table) = & i960_cgen_operand_table[0];
|
|
|
|
* CGEN_OPCODE_INSN_TABLE (table) = insn_table;
|
|
|
|
* CGEN_OPCODE_MACRO_INSN_TABLE (table) = macro_insn_table;
|
|
|
|
CGEN_OPCODE_ASM_HASH_P (table) = asm_hash_insn_p;
|
|
CGEN_OPCODE_ASM_HASH (table) = asm_hash_insn;
|
|
CGEN_OPCODE_ASM_HASH_SIZE (table) = CGEN_ASM_HASH_SIZE;
|
|
|
|
CGEN_OPCODE_DIS_HASH_P (table) = dis_hash_insn_p;
|
|
CGEN_OPCODE_DIS_HASH (table) = dis_hash_insn;
|
|
CGEN_OPCODE_DIS_HASH_SIZE (table) = CGEN_DIS_HASH_SIZE;
|
|
|
|
return (CGEN_OPCODE_DESC) table;
|
|
}
|
|
|
|
/* Close an opcode table. */
|
|
|
|
void
|
|
i960_cgen_opcode_close (desc)
|
|
CGEN_OPCODE_DESC desc;
|
|
{
|
|
free (desc);
|
|
}
|
|
|
|
/* Getting values from cgen_fields is handled by a collection of functions.
|
|
They are distinguished by the type of the VALUE argument they return.
|
|
TODO: floating point, inlining support, remove cases where result type
|
|
not appropriate. */
|
|
|
|
int
|
|
i960_cgen_get_int_operand (opindex, fields)
|
|
int opindex;
|
|
const CGEN_FIELDS * fields;
|
|
{
|
|
int value;
|
|
|
|
switch (opindex)
|
|
{
|
|
case I960_OPERAND_SRC1 :
|
|
value = fields->f_src1;
|
|
break;
|
|
case I960_OPERAND_SRC2 :
|
|
value = fields->f_src2;
|
|
break;
|
|
case I960_OPERAND_DST :
|
|
value = fields->f_srcdst;
|
|
break;
|
|
case I960_OPERAND_LIT1 :
|
|
value = fields->f_src1;
|
|
break;
|
|
case I960_OPERAND_LIT2 :
|
|
value = fields->f_src2;
|
|
break;
|
|
case I960_OPERAND_ST_SRC :
|
|
value = fields->f_srcdst;
|
|
break;
|
|
case I960_OPERAND_ABASE :
|
|
value = fields->f_abase;
|
|
break;
|
|
case I960_OPERAND_OFFSET :
|
|
value = fields->f_offset;
|
|
break;
|
|
case I960_OPERAND_SCALE :
|
|
value = fields->f_scale;
|
|
break;
|
|
case I960_OPERAND_INDEX :
|
|
value = fields->f_index;
|
|
break;
|
|
case I960_OPERAND_OPTDISP :
|
|
value = fields->f_optdisp;
|
|
break;
|
|
case I960_OPERAND_BR_SRC1 :
|
|
value = fields->f_br_src1;
|
|
break;
|
|
case I960_OPERAND_BR_SRC2 :
|
|
value = fields->f_br_src2;
|
|
break;
|
|
case I960_OPERAND_BR_DISP :
|
|
value = fields->f_br_disp;
|
|
break;
|
|
case I960_OPERAND_BR_LIT1 :
|
|
value = fields->f_br_src1;
|
|
break;
|
|
case I960_OPERAND_CTRL_DISP :
|
|
value = fields->f_ctrl_disp;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
bfd_vma
|
|
i960_cgen_get_vma_operand (opindex, fields)
|
|
int opindex;
|
|
const CGEN_FIELDS * fields;
|
|
{
|
|
bfd_vma value;
|
|
|
|
switch (opindex)
|
|
{
|
|
case I960_OPERAND_SRC1 :
|
|
value = fields->f_src1;
|
|
break;
|
|
case I960_OPERAND_SRC2 :
|
|
value = fields->f_src2;
|
|
break;
|
|
case I960_OPERAND_DST :
|
|
value = fields->f_srcdst;
|
|
break;
|
|
case I960_OPERAND_LIT1 :
|
|
value = fields->f_src1;
|
|
break;
|
|
case I960_OPERAND_LIT2 :
|
|
value = fields->f_src2;
|
|
break;
|
|
case I960_OPERAND_ST_SRC :
|
|
value = fields->f_srcdst;
|
|
break;
|
|
case I960_OPERAND_ABASE :
|
|
value = fields->f_abase;
|
|
break;
|
|
case I960_OPERAND_OFFSET :
|
|
value = fields->f_offset;
|
|
break;
|
|
case I960_OPERAND_SCALE :
|
|
value = fields->f_scale;
|
|
break;
|
|
case I960_OPERAND_INDEX :
|
|
value = fields->f_index;
|
|
break;
|
|
case I960_OPERAND_OPTDISP :
|
|
value = fields->f_optdisp;
|
|
break;
|
|
case I960_OPERAND_BR_SRC1 :
|
|
value = fields->f_br_src1;
|
|
break;
|
|
case I960_OPERAND_BR_SRC2 :
|
|
value = fields->f_br_src2;
|
|
break;
|
|
case I960_OPERAND_BR_DISP :
|
|
value = fields->f_br_disp;
|
|
break;
|
|
case I960_OPERAND_BR_LIT1 :
|
|
value = fields->f_br_src1;
|
|
break;
|
|
case I960_OPERAND_CTRL_DISP :
|
|
value = fields->f_ctrl_disp;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
|
|
return value;
|
|
}
|
|
|
|
/* Stuffing values in cgen_fields is handled by a collection of functions.
|
|
They are distinguished by the type of the VALUE argument they accept.
|
|
TODO: floating point, inlining support, remove cases where argument type
|
|
not appropriate. */
|
|
|
|
void
|
|
i960_cgen_set_int_operand (opindex, fields, value)
|
|
int opindex;
|
|
CGEN_FIELDS * fields;
|
|
int value;
|
|
{
|
|
switch (opindex)
|
|
{
|
|
case I960_OPERAND_SRC1 :
|
|
fields->f_src1 = value;
|
|
break;
|
|
case I960_OPERAND_SRC2 :
|
|
fields->f_src2 = value;
|
|
break;
|
|
case I960_OPERAND_DST :
|
|
fields->f_srcdst = value;
|
|
break;
|
|
case I960_OPERAND_LIT1 :
|
|
fields->f_src1 = value;
|
|
break;
|
|
case I960_OPERAND_LIT2 :
|
|
fields->f_src2 = value;
|
|
break;
|
|
case I960_OPERAND_ST_SRC :
|
|
fields->f_srcdst = value;
|
|
break;
|
|
case I960_OPERAND_ABASE :
|
|
fields->f_abase = value;
|
|
break;
|
|
case I960_OPERAND_OFFSET :
|
|
fields->f_offset = value;
|
|
break;
|
|
case I960_OPERAND_SCALE :
|
|
fields->f_scale = value;
|
|
break;
|
|
case I960_OPERAND_INDEX :
|
|
fields->f_index = value;
|
|
break;
|
|
case I960_OPERAND_OPTDISP :
|
|
fields->f_optdisp = value;
|
|
break;
|
|
case I960_OPERAND_BR_SRC1 :
|
|
fields->f_br_src1 = value;
|
|
break;
|
|
case I960_OPERAND_BR_SRC2 :
|
|
fields->f_br_src2 = value;
|
|
break;
|
|
case I960_OPERAND_BR_DISP :
|
|
fields->f_br_disp = value;
|
|
break;
|
|
case I960_OPERAND_BR_LIT1 :
|
|
fields->f_br_src1 = value;
|
|
break;
|
|
case I960_OPERAND_CTRL_DISP :
|
|
fields->f_ctrl_disp = value;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
}
|
|
|
|
void
|
|
i960_cgen_set_vma_operand (opindex, fields, value)
|
|
int opindex;
|
|
CGEN_FIELDS * fields;
|
|
bfd_vma value;
|
|
{
|
|
switch (opindex)
|
|
{
|
|
case I960_OPERAND_SRC1 :
|
|
fields->f_src1 = value;
|
|
break;
|
|
case I960_OPERAND_SRC2 :
|
|
fields->f_src2 = value;
|
|
break;
|
|
case I960_OPERAND_DST :
|
|
fields->f_srcdst = value;
|
|
break;
|
|
case I960_OPERAND_LIT1 :
|
|
fields->f_src1 = value;
|
|
break;
|
|
case I960_OPERAND_LIT2 :
|
|
fields->f_src2 = value;
|
|
break;
|
|
case I960_OPERAND_ST_SRC :
|
|
fields->f_srcdst = value;
|
|
break;
|
|
case I960_OPERAND_ABASE :
|
|
fields->f_abase = value;
|
|
break;
|
|
case I960_OPERAND_OFFSET :
|
|
fields->f_offset = value;
|
|
break;
|
|
case I960_OPERAND_SCALE :
|
|
fields->f_scale = value;
|
|
break;
|
|
case I960_OPERAND_INDEX :
|
|
fields->f_index = value;
|
|
break;
|
|
case I960_OPERAND_OPTDISP :
|
|
fields->f_optdisp = value;
|
|
break;
|
|
case I960_OPERAND_BR_SRC1 :
|
|
fields->f_br_src1 = value;
|
|
break;
|
|
case I960_OPERAND_BR_SRC2 :
|
|
fields->f_br_src2 = value;
|
|
break;
|
|
case I960_OPERAND_BR_DISP :
|
|
fields->f_br_disp = value;
|
|
break;
|
|
case I960_OPERAND_BR_LIT1 :
|
|
fields->f_br_src1 = value;
|
|
break;
|
|
case I960_OPERAND_CTRL_DISP :
|
|
fields->f_ctrl_disp = value;
|
|
break;
|
|
|
|
default :
|
|
/* xgettext:c-format */
|
|
fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"),
|
|
opindex);
|
|
abort ();
|
|
}
|
|
}
|
|
|