mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-12-23 17:23:29 +08:00
f5555712ba
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64.h (aarch64_op): Remove OP_V_MOVI_B. opcodes/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI. * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise. * aarch64-opc.c (operand_general_constraint_met_p): For AARCH64_MOD_LSL, move the range check on the shift amount before the alignment check; change to call set_sft_amount_out_of_range_error instead of set_imm_out_of_range_error. * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL. (aarch64_opcode_table): Remove the OP enumerator from the asimdimm 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to SIMD_IMM_SFT. gas/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * config/tc-aarch64.c (output_operand_error_record): Change to output the out-of-range error message as value-expected message if there is only one single value in the expected range. (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with LSL #0 as a programmer-friendly feature. gas/testsuite/ 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com> * gas/aarch64/diagnostic.l: Update. * gas/aarch64/movi.s: Add tests. * gas/aarch64/movi.d: Update. * gas/aarch64/programmer-friendly.s: Add comment.
115 lines
4.0 KiB
Plaintext
115 lines
4.0 KiB
Plaintext
2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
|
||
|
||
* aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
|
||
* aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
|
||
* aarch64-opc.c (operand_general_constraint_met_p): For
|
||
AARCH64_MOD_LSL, move the range check on the shift amount before the
|
||
alignment check; change to call set_sft_amount_out_of_range_error
|
||
instead of set_imm_out_of_range_error.
|
||
* aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
|
||
(aarch64_opcode_table): Remove the OP enumerator from the asimdimm
|
||
8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
|
||
SIMD_IMM_SFT.
|
||
|
||
2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
|
||
|
||
* i386-init.h: Regenerated.
|
||
* i386-tbl.h: Likewise.
|
||
|
||
2013-01-15 Nick Clifton <nickc@redhat.com>
|
||
|
||
* v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
|
||
values.
|
||
* v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
|
||
|
||
2013-01-14 Will Newton <will.newton@imgtec.com>
|
||
|
||
* metag-dis.c (REG_WIDTH): Increase to 64.
|
||
|
||
2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
|
||
|
||
* ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
|
||
* ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
|
||
XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
|
||
(SH6): Update.
|
||
<"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
|
||
"tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
|
||
"treclaim.", "tsr.">: Add POWER8 HTM opcodes.
|
||
<"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
|
||
|
||
2013-01-10 Will Newton <will.newton@imgtec.com>
|
||
|
||
* Makefile.am: Add Meta.
|
||
* configure.in: Add Meta.
|
||
* disassemble.c: Add Meta support.
|
||
* metag-dis.c: New file.
|
||
* Makefile.in: Regenerate.
|
||
* configure: Regenerate.
|
||
|
||
2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
|
||
|
||
* cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
|
||
(match_opcode): Rename to cr16_match_opcode.
|
||
|
||
2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
|
||
|
||
* mips-dis.c: Add names for CP0 registers of r5900.
|
||
* mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
|
||
instructions sq and lq.
|
||
Add support for MIPS r5900 CPU.
|
||
Add support for 128 bit MMI (Multimedia Instructions).
|
||
Add support for EE instructions (Emotion Engine).
|
||
Disable unsupported floating point instructions (64 bit and
|
||
undefined compare operations).
|
||
Enable instructions of MIPS ISA IV which are supported by r5900.
|
||
Disable 64 bit co processor instructions.
|
||
Disable 64 bit multiplication and division instructions.
|
||
Disable instructions for co-processor 2 and 3, because these are
|
||
not supported (preparation for later VU0 support (Vector Unit)).
|
||
Disable cvt.w.s because this behaves like trunc.w.s and the
|
||
correct execution can't be ensured on r5900.
|
||
Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
|
||
will confuse less developers and compilers.
|
||
|
||
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_print_operand): Change to print
|
||
AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
|
||
in comment.
|
||
* aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
|
||
from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
|
||
OP_MOV_IMM_WIDE.
|
||
|
||
2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
|
||
|
||
* aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
|
||
PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
|
||
|
||
2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
|
||
|
||
* i386-gen.c (process_copyright): Update copyright year to 2013.
|
||
|
||
2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
|
||
|
||
* cr16-dis.c (match_opcode,make_instruction): Remove static
|
||
declaration.
|
||
(dwordU,wordU): Moved typedefs to opcode/cr16.h
|
||
(cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
|
||
|
||
For older changes see ChangeLog-2012
|
||
|
||
Copyright (C) 2013 Free Software Foundation, Inc.
|
||
|
||
Copying and distribution of this file, with or without modification,
|
||
are permitted in any medium without royalty provided the copyright
|
||
notice and this notice are preserved.
|
||
|
||
Local Variables:
|
||
mode: change-log
|
||
left-margin: 8
|
||
fill-column: 74
|
||
version-control: never
|
||
End:
|