Jeff Law b3fa92f12a Yet another fix for mcore-sim (rotli) ... This came up testing the CRC optimization work from Mariam@RAU. Basically to optimize some CRC loops into table lookups or carryless multiplies, we may need to do a bit reflection, which on the mcore processor is done using a rotate instruction. Unfortunately the simulator implementation of rotates has the exact same problem as we saw with right shifts. The input value may have been sign extended from 32 to 64 bits. When we rotate the extended value, we get those sign extension bits and thus the wrong result. The fix is the same. Rather than using a "long", use a uint32_t for the type of the temporary. This fixes a handful of tests in the GCC testsuite:		2023-12-18 22:04:25 -07:00
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aarch64	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
arm	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
avr	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
bfin	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
bpf	sim: bpf: do not use semicolon to begin comments	2023-11-28 15:01:18 +01:00
common	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
config	sim: testsuite: rework sim_init usage	2021-11-26 19:48:05 -05:00
cr16	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
cris	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
d10v	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
example-synacor	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
frv	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
ft32	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
h8300	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
iq2000	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
lib	sim prune_warnings	2023-08-19 12:41:32 +09:30
lm32	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
m32c	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
m32r	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
m68hc11	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
mcore	Yet another fix for mcore-sim (rotli)	2023-12-18 22:04:25 -07:00
microblaze	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
mips	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
mn10300	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
moxie	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
msp430	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
or1k	sim: or1k: Eliminate dangerous RWX load segments	2023-08-24 07:03:48 +01:00
pru	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00
riscv	sim/riscv: fix JALR instruction simulation	2023-10-18 17:55:31 +01:00
sh	sim: testsuite: cleanup the istarget * logic	2022-02-16 00:36:47 -05:00
v850	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
.gitignore
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
local.mk	Update copyright year range in header of all files managed by GDB	2023-01-01 17:01:16 +04:00