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binutils-gdb/opcodes/aarch64-asm.h
Tamar Christina 561a72d4dd Modify AArch64 Assembly and disassembly functions to be able to fail and report why. 
This patch if the first patch in a series to add the ability to add constraints
to system registers that an instruction must adhere to in order for the register
to be usable with that instruction.

These constraints can also be used to disambiguate between registers with the
same encoding during disassembly.

This patch adds a new flags entry in the sysreg structures and ensures it is
filled in and read out during assembly/disassembly. It also adds the ability for
the assemble and disassemble functions to be able to gracefully fail and re-use
the existing error reporting infrastructure.

The return type of these functions are changed to a boolean to denote success or
failure and the error structure is passed around to them. This requires
aarch64-gen changes so a lot of the changes here are just mechanical.

gas/

	PR binutils/21446
	* config/tc-aarch64.c (parse_sys_reg): Return register flags.
	(parse_operands): Fill in register flags.

gdb/

	PR binutils/21446
	* aarch64-tdep.c (aarch64_analyze_prologue,
	aarch64_software_single_step, aarch64_displaced_step_copy_insn):
	Indicate not interested in errors.

include/

	PR binutils/21446
	* opcode/aarch64.h (aarch64_opnd_info): Change sysreg to struct.
	(aarch64_decode_insn): Accept error struct.

opcodes/

	PR binutils/21446
	* aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
	and take error struct.
	* aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
	aarch64_ins_reglist, aarch64_ins_ldst_reglist,
	aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
	aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
	aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
	aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
	aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
	aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
	aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
	aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
	aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
	aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
	aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
	aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
	aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
	aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
	aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
	aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
	aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
	aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
	aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
	aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
	aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
	aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
	* aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
	* aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
	aarch64_ext_reglist, aarch64_ext_ldst_reglist,
	aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
	aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
	aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
	aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
	aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
	aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
	aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
	aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
	aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
	aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
	aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
	aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
	aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
	aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
	aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
	aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
	aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
	aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
	aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
	aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
	aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
	aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
	aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
	(determine_disassembling_preference, aarch64_decode_insn,
	print_insn_aarch64_word, print_insn_data): Take errors struct.
	(print_insn_aarch64): Use errors.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-gen.c (print_operand_inserter): Use errors and change type to
	boolean in aarch64_insert_operan.
	(print_operand_extractor): Likewise.
	* aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
2018-05-15 17:17:36 +01:00

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/* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
Copyright (C) 2012-2018 Free Software Foundation, Inc.
Contributed by ARM Ltd.
This file is part of the GNU opcodes library.
This library is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3, or (at your option)
any later version.
It is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
#ifndef OPCODES_AARCH64_ASM_H
#define OPCODES_AARCH64_ASM_H
#include "aarch64-opc.h"
/* Given OPCODE, return the opcode entry that OPCODE aliases to, e.g.
given LSL, return UBFM. */
const aarch64_opcode* aarch64_find_real_opcode (const aarch64_opcode *);
/* Switch-table-based high-level operand inserter. */
bfd_boolean aarch64_insert_operand (const aarch64_operand *,
const aarch64_opnd_info *, aarch64_insn *,
const aarch64_inst *,
aarch64_operand_error *);
/* Operand inserters. */
#define AARCH64_DECL_OPD_INSERTER(x) \
bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
aarch64_insn *, const aarch64_inst *, \
aarch64_operand_error *)
AARCH64_DECL_OPD_INSERTER (ins_regno);
AARCH64_DECL_OPD_INSERTER (ins_reglane);
AARCH64_DECL_OPD_INSERTER (ins_reglist);
AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist);
AARCH64_DECL_OPD_INSERTER (ins_ldst_reglist_r);
AARCH64_DECL_OPD_INSERTER (ins_ldst_elemlist);
AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_shift);
AARCH64_DECL_OPD_INSERTER (ins_imm);
AARCH64_DECL_OPD_INSERTER (ins_imm_half);
AARCH64_DECL_OPD_INSERTER (ins_advsimd_imm_modified);
AARCH64_DECL_OPD_INSERTER (ins_fpimm);
AARCH64_DECL_OPD_INSERTER (ins_fbits);
AARCH64_DECL_OPD_INSERTER (ins_aimm);
AARCH64_DECL_OPD_INSERTER (ins_limm);
AARCH64_DECL_OPD_INSERTER (ins_inv_limm);
AARCH64_DECL_OPD_INSERTER (ins_ft);
AARCH64_DECL_OPD_INSERTER (ins_addr_simple);
AARCH64_DECL_OPD_INSERTER (ins_addr_offset);
AARCH64_DECL_OPD_INSERTER (ins_addr_regoff);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm);
AARCH64_DECL_OPD_INSERTER (ins_addr_simm10);
AARCH64_DECL_OPD_INSERTER (ins_addr_uimm12);
AARCH64_DECL_OPD_INSERTER (ins_simd_addr_post);
AARCH64_DECL_OPD_INSERTER (ins_cond);
AARCH64_DECL_OPD_INSERTER (ins_sysreg);
AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
AARCH64_DECL_OPD_INSERTER (ins_barrier);
AARCH64_DECL_OPD_INSERTER (ins_hint);
AARCH64_DECL_OPD_INSERTER (ins_prfop);
AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s9xvl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_u6);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rr_lsl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_rz_xtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zi_u5);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_lsl);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_sxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_addr_zz_uxtw);
AARCH64_DECL_OPD_INSERTER (ins_sve_aimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_asimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_half_two);
AARCH64_DECL_OPD_INSERTER (ins_sve_float_zero_one);
AARCH64_DECL_OPD_INSERTER (ins_sve_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
AARCH64_DECL_OPD_INSERTER (ins_sve_shrimm);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
#undef AARCH64_DECL_OPD_INSERTER
#endif /* OPCODES_AARCH64_ASM_H */
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