Jeff Law 477904ca75 Fix for v850e divq instruction ... This is the last of the correctness fixes I've been carrying around for the v850. Like the other recent fixes, this is another case where we haven't been as careful as we should WRT host vs target types. For the divq instruction both operands are 32 bit types. Yet in the simulator code we convert them from unsigned int to signed long by assignment. So 0xfffffffb (aka -5) turns into 4294967291 and naturally that changes the result of our division. The fix is simple, insert a cast to int32_t to force interpretation as a signed value. Testcase for the simulator is included. It has a trivial dependency on the bins patch.		2022-04-06 11:10:40 -04:00
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allinsns.exp	Fix "bins" simulation for v850e3v5	2022-04-06 11:06:53 -04:00
bins.cgs	Fix "bins" simulation for v850e3v5	2022-04-06 11:06:53 -04:00
bsh.cgs
ChangeLog-2021	sim: rename ChangeLog files to ChangeLog-2021	2021-08-17 20:27:36 -04:00
div.cgs
divh_3.cgs
divh.cgs
divhu.cgs
divq.cgs	Fix for v850e divq instruction	2022-04-06 11:10:40 -04:00
divu.cgs
mul.cgs	Fix for MUL instruction on the v850	2022-03-29 20:08:35 -04:00
sar.cgs
satadd.cgs
satsub.cgs
satsubi.cgs
satsubr.cgs
shl.cgs
shr.cgs
testutils.cgs
testutils.inc