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ef9d256562
2021-05-31 Nelson Chu <nelson.chu@sifive.com>
Lifang Xia <lifang_xia@c-sky.com>
The data segment phase exp_seg_relro_adjust means we are still adjusting the
relro segments, so we will get the symbol values which havn't consider the
relro. It is dangerous and we shouldn't do the relaxations at this stage.
Otherwise, we may get the truncated fails when the relax range crossing the
data segment.
One of the solution is that, we use a pointer to monitor the data segment
phase while relaxing, to know whether the relro has been handled or not.
Once we check the phase is exp_seg_relro_adjust, we should skip this round
of relaxations, since the incorrect symbol values will affect the correctness
of relaxations. I think we probably need to record more information about
data segment or alignments in the future, to make sure it is safe to doing
relaxations.
For the two new testcases, relro-relax-lui and relro-relax-pcrel, we get
the following truncated errors when using toolchains, which enable relro:
(.text+0x0): relocation truncated to fit: R_RISCV_GPREL_I against symbol `SymbolRodata' defined in .rodata section in test1.o
After applying this patch, the truncated errors should be resolved.
However, only linux toolchains support -z relro, so we only test these
two testcases when supporting shared library.
bfd/
PR 27566
* elfnn-riscv.c (struct riscv_elf_link_hash_table): New integer pointer
to monitor the data segment phase.
(bfd_elfNN_riscv_set_data_segment_info): New function called by
after_allocation, to set the data_segment_phase from expld.dataseg.
(_bfd_riscv_relax_section): Don't relax when data_segment_phase is
exp_seg_relro_adjust (0x4).
* elfxx-riscv.h (bfd_elf32_riscv_set_data_segment_info): New extern.
(bfd_elf64_riscv_set_data_segment_info): Likewise.
ld/
PR 27566
* emultempl/riscvelf.em (after_allocation): Call
riscv_set_data_segment_info to set data segment phase before relaxing.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
* testsuite/ld-riscv-elf/relro-relax-lui.d: New testcase.
* testsuite/ld-riscv-elf/relro-relax-lui.s: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.d: Likewise.
* testsuite/ld-riscv-elf/relro-relax-pcrel.s: Likewise.
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| .. | ||
| aarch64elf.em | ||
| aix.em | ||
| alphaelf.em | ||
| arclinux.em | ||
| armcoff.em | ||
| armelf.em | ||
| astring.sed | ||
| avrelf.em | ||
| beos.em | ||
| bfin.em | ||
| cr16elf.em | ||
| crxelf.em | ||
| cskyelf.em | ||
| elf-generic.em | ||
| elf-x86.em | ||
| elf.em | ||
| epiphanyelf_4x4.em | ||
| genelf.em | ||
| generic.em | ||
| hppaelf.em | ||
| ia64elf.em | ||
| irix.em | ||
| linux.em | ||
| m68hc1xelf.em | ||
| m68kelf.em | ||
| metagelf.em | ||
| mipself.em | ||
| mmix-elfnmmo.em | ||
| mmixelf.em | ||
| mmo.em | ||
| msp430.em | ||
| nds32elf.em | ||
| needrelax.em | ||
| netbsd.em | ||
| nios2elf.em | ||
| ostring.sed | ||
| pdp11.em | ||
| pe.em | ||
| pep.em | ||
| ppc32elf.em | ||
| ppc64elf.em | ||
| pruelf.em | ||
| README | ||
| riscvelf.em | ||
| rxelf.em | ||
| rxlinux.em | ||
| s390.em | ||
| scoreelf.em | ||
| solaris2-x86.em | ||
| solaris2.em | ||
| spu_icache.o_c | ||
| spu_icache.S | ||
| spu_ovl.o_c | ||
| spu_ovl.S | ||
| spuelf.em | ||
| tic6xdsbt.em | ||
| ticoff.em | ||
| v850elf.em | ||
| vanilla.em | ||
| vms.em | ||
| vxworks.em | ||
| xtensaelf.em | ||
| z80.em | ||
The files in this directory are sourced by genscripts.sh, after
setting some variables to substitute in, to produce
C source files that contain jump tables for each emulation.
Copyright (C) 2012-2021 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.