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b138abaa40
(my_get_expression): Const operand of some instructions can not be symbol in assembly. (get_insn_class_from_type): Handle instruction type Insn_internal. (do_macro_ldst_label): Modify inst.type. (Insn_PIC): Delete. * score-inst.h (enum score_insn_type): Add Insn_internal. * tc-score.c (data_op2): The immediate value in lw is 15 bit signed. * score-dis.c (print_insn): Correct the error code to print correct PCE instruction disassembly.
505 lines
16 KiB
C
505 lines
16 KiB
C
/* Instruction printing code for Score
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Copyright 2006 Free Software Foundation, Inc.
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Contributed by:
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Mei Ligang (ligang@sunnorth.com.cn)
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Pei-Lin Tsai (pltsai@sunplus.com)
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This file is part of libopcodes.
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This program is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#define DEFINE_TABLE
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#include "score-opc.h"
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#include "opintl.h"
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#include "bfd.h"
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/* FIXME: This shouldn't be done here. */
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#include "elf-bfd.h"
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#include "elf/internal.h"
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#include "elf/score.h"
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#ifndef streq
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#define streq(a,b) (strcmp ((a), (b)) == 0)
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#endif
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#ifndef strneq
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#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
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#endif
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#ifndef NUM_ELEM
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#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
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#endif
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typedef struct
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{
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const char *name;
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const char *description;
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const char *reg_names[32];
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} score_regname;
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static score_regname regnames[] =
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{
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{"gcc", "Select register names used by GCC",
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
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"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
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"r21", "r22", "r23", "r24", "r25", "r26", "r27", "gp", "r29", "r30", "r31"}},
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};
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static unsigned int regname_selected = 0;
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#define NUM_SCORE_REGNAMES NUM_ELEM (regnames)
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#define score_regnames regnames[regname_selected].reg_names
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction. */
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static int
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print_insn_score32 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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struct score_opcode *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = score_opcodes; insn->assembler; insn++)
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{
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if ((insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
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{
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char *c;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case 'j':
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{
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int target;
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if (info->flags & INSN_HAS_RELOC)
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pc = 0;
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target = (pc & 0xfe000000) | (given & 0x01fffffe);
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(*info->print_address_func) (target, info);
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}
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break;
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case 'b':
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{
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/* Sign-extend a 20-bit number. */
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#define SEXT20(x) ((((x) & 0xfffff) ^ (~ 0x7ffff)) + 0x80000)
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int disp = ((given & 0x01ff8000) >> 5) | (given & 0x3fe);
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int target = (pc + SEXT20 (disp));
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(*info->print_address_func) (target, info);
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}
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break;
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case '0':
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case '1':
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case '2':
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case '3':
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case '4':
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case '5':
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case '6':
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case '7':
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case '8':
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case '9':
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{
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int bitstart = *c++ - '0';
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int bitend = 0;
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while (*c >= '0' && *c <= '9')
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bitstart = (bitstart * 10) + *c++ - '0';
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switch (*c)
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{
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case '-':
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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if (!bitend)
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abort ();
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switch (*c)
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{
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case 'r':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%s", score_regnames[reg]);
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}
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break;
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case 'd':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%ld", reg);
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}
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break;
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case 'i':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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reg = ((reg ^ (1 << (bitend - bitstart))) -
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(1 << (bitend - bitstart)));
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if (((given & insn->mask) == 0x0c00000a) /* ldc1 */
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|| ((given & insn->mask) == 0x0c000012) /* ldc2 */
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|| ((given & insn->mask) == 0x0c00001c) /* ldc3 */
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|| ((given & insn->mask) == 0x0c00000b) /* stc1 */
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|| ((given & insn->mask) == 0x0c000013) /* stc2 */
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|| ((given & insn->mask) == 0x0c00001b)) /* stc3 */
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reg <<= 2;
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func (stream, "%ld", reg);
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}
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break;
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case 'x':
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{
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long reg;
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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func (stream, "%lx", reg);
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}
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break;
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default:
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abort ();
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}
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break;
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case '`':
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c++;
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if ((given & (1 << bitstart)) == 0)
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func (stream, "%c", *c);
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break;
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case '\'':
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c++;
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if ((given & (1 << bitstart)) != 0)
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func (stream, "%c", *c);
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break;
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default:
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abort ();
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}
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break;
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default:
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abort ();
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}
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}
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}
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else
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func (stream, "%c", *c);
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}
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return 4;
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}
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}
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#if (SCORE_SIMULATOR_ACTIVE)
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func (stream, _("<illegal instruction>"));
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return 4;
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#endif
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abort ();
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}
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static void
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print_insn_parallel_sym (struct disassemble_info *info)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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/* 10: 0000 nop!
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4 space + 1 colon + 1 space + 1 tab + 8 opcode + 2 space + 1 tab.
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FIXME: the space number is not accurate. */
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func (stream, "%s", " ||\n \t \t");
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}
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/* Print one instruction from PC on INFO->STREAM.
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Return the size of the instruction. */
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static int
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print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
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{
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struct score_opcode *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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given &= 0xffff;
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for (insn = score_opcodes; insn->assembler; insn++)
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{
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if (!(insn->mask & 0xffff0000) && (given & insn->mask) == insn->value)
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{
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char *c = insn->assembler;
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info->bytes_per_chunk = 2;
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info->bytes_per_line = 4;
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given &= 0xffff;
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for (; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case 'j':
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{
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int target;
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if (info->flags & INSN_HAS_RELOC)
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pc = 0;
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target = (pc & 0xfffff000) | (given & 0x00000ffe);
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(*info->print_address_func) (target, info);
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}
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break;
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case 'b':
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{
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/* Sign-extend a 9-bit number. */
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#define SEXT9(x) ((((x) & 0x1ff) ^ (~ 0xff)) + 0x100)
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int disp = (given & 0xff) << 1;
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int target = (pc + SEXT9 (disp));
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(*info->print_address_func) (target, info);
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}
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break;
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case '0':
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case '1':
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case '2':
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case '3':
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case '4':
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case '5':
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case '6':
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case '7':
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case '8':
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case '9':
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{
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int bitstart = *c++ - '0';
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int bitend = 0;
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while (*c >= '0' && *c <= '9')
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bitstart = (bitstart * 10) + *c++ - '0';
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switch (*c)
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{
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case '-':
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{
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long reg;
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c++;
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while (*c >= '0' && *c <= '9')
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bitend = (bitend * 10) + *c++ - '0';
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if (!bitend)
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abort ();
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reg = given >> bitstart;
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reg &= (2 << (bitend - bitstart)) - 1;
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switch (*c)
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{
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case 'R':
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func (stream, "%s", score_regnames[reg + 16]);
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break;
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case 'r':
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func (stream, "%s", score_regnames[reg]);
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break;
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case 'd':
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if (*(c + 1) == '\0')
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func (stream, "%ld", reg);
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else
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{
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c++;
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if (*c == '1')
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func (stream, "%ld", reg << 1);
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else if (*c == '2')
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func (stream, "%ld", reg << 2);
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}
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break;
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case 'x':
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if (*(c + 1) == '\0')
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func (stream, "%lx", reg);
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else
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{
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c++;
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if (*c == '1')
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func (stream, "%lx", reg << 1);
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else if (*c == '2')
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func (stream, "%lx", reg << 2);
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}
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break;
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case 'i':
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reg = ((reg ^ (1 << bitend)) - (1 << bitend));
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func (stream, "%ld", reg);
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break;
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default:
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abort ();
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}
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}
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break;
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case '\'':
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c++;
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if ((given & (1 << bitstart)) != 0)
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func (stream, "%c", *c);
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break;
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default:
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abort ();
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}
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}
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break;
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default:
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abort ();
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}
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}
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else
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func (stream, "%c", *c);
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}
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return 2;
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}
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}
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#if (SCORE_SIMULATOR_ACTIVE)
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func (stream, _("<illegal instruction>"));
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return 2;
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#endif
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/* No match. */
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abort ();
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}
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/* NOTE: There are no checks in these routines that
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the relevant number of data bytes exist. */
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static int
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print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
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{
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unsigned char b[4];
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long given;
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long ridparity;
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int status;
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bfd_boolean insn_pce_p = FALSE;
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bfd_boolean insn_16_p = FALSE;
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info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
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if (pc & 0x2)
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{
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info->bytes_per_chunk = 2;
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status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
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b[3] = b[2] = 0;
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insn_16_p = TRUE;
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}
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else
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{
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info->bytes_per_chunk = 4;
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status = info->read_memory_func (pc, (bfd_byte *) & b[0], 4, info);
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if (status != 0)
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{
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info->bytes_per_chunk = 2;
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status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
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b[3] = b[2] = 0;
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insn_16_p = TRUE;
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}
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}
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if (status != 0)
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{
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info->memory_error_func (status, pc, info);
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return -1;
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}
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if (little)
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{
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given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
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}
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else
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{
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given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]);
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}
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if ((given & 0x80008000) == 0x80008000)
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{
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insn_pce_p = FALSE;
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insn_16_p = FALSE;
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}
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else if ((given & 0x8000) == 0x8000)
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{
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insn_pce_p = TRUE;
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}
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else
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{
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insn_16_p = TRUE;
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}
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/* 16 bit instruction. */
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if (insn_16_p)
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{
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if (little)
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{
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given = b[0] | (b[1] << 8);
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}
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else
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{
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given = (b[0] << 8) | b[1];
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}
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status = print_insn_score16 (pc, info, given);
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}
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/* pce instruction. */
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else if (insn_pce_p)
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{
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long other;
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other = given & 0xFFFF;
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given = (given & 0xFFFF0000) >> 16;
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status = print_insn_score16 (pc, info, given);
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print_insn_parallel_sym (info);
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status += print_insn_score16 (pc, info, other);
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/* disassemble_bytes() will output 4 byte per chunk for pce instructio. */
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info->bytes_per_chunk = 4;
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}
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/* 32 bit instruction. */
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else
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{
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/* Get rid of parity. */
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ridparity = (given & 0x7FFF);
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ridparity |= (given & 0x7FFF0000) >> 1;
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given = ridparity;
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status = print_insn_score32 (pc, info, given);
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}
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return status;
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}
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int
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print_insn_big_score (bfd_vma pc, struct disassemble_info *info)
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{
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return print_insn (pc, info, FALSE);
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}
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int
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print_insn_little_score (bfd_vma pc, struct disassemble_info *info)
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{
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return print_insn (pc, info, TRUE);
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}
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