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65dcce8f79
binutils-gdb/sim
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Mike Frysinger 65dcce8f79 sim: add arch-specific conditional logic 
This will make it easy to include arch-specific logic (build files)
as we migrate ports to the common top level build.
2021-10-31 02:03:16 -04:00
..
aarch64 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
arm sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
avr sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
bfin sim: filter out SIGSTKSZ [PR sim/28302] 2021-10-03 12:02:53 -04:00
bpf sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
common sim: common: merge multiple clean commands 2021-10-31 01:17:10 -04:00
cr16 sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
cris sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
d10v sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
erc32 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
example-synacor sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
frv sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
ft32 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
h8300 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
igen sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
iq2000 sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
lm32 sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
m4 sim: bfin: add support for SDL2 2021-09-13 22:45:19 -04:00
m32c sim: m32c: tighten up opc2c build output 2021-10-31 01:11:41 -04:00
m32r sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
m68hc11 sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
mcore sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
microblaze sim: microblaze: replace custom basic types with common ones 2021-09-08 21:32:34 -04:00
mips sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
mn10300 sim: igen: tighten up build output 2021-10-31 00:55:50 -04:00
moxie sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
msp430 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
or1k sim: tighten up stamp rules 2021-10-31 00:49:39 -04:00
ppc sim: silence stamp touch rules 2021-10-31 00:46:28 -04:00
pru sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
riscv sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
rl78 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
rx sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
sh sim: tighten up gencode output 2021-10-31 01:05:27 -04:00
testsuite sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
v850 sim: v850: delete old gencode logic 2021-10-31 01:49:17 -04:00
.gitignore sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
aclocal.m4 sim: unify reserved instruction bits settings 2021-07-01 20:53:00 -04:00
arch-subdir.mk.in sim: ppc: fallback when ln is not available [PR sim/18864] 2021-10-03 11:36:30 -04:00
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
config.h.in sim: bfin: add support for SDL2 2021-09-13 22:45:19 -04:00
configure sim: add arch-specific conditional logic 2021-10-31 02:03:16 -04:00
configure.ac sim: add arch-specific conditional logic 2021-10-31 02:03:16 -04:00
MAINTAINERS sim: readd myself as a maintainer 2021-01-29 22:11:45 -05:00
Makefile.am sim: nltvals: switch output mode to a directory 2021-08-19 21:05:28 -04:00
Makefile.in sim: nltvals: switch output mode to a directory 2021-08-19 21:05:28 -04:00
README-HACKING sim: hw: rework configure option & device selection 2021-06-21 21:36:51 -04:00