binutils-gdb/sim/testsuite/mips/basic.exp
Faraz Shahbazker 06c441ccef sim: mips: Add simulator support for mips32r6/mips64r6
2022-02-01  Ali Lown  <ali.lown@imgtec.com>
	    Andrew Bennett  <andrew.bennett@imgtec.com>
	    Dragan Mladjenovic  <dragan.mladjenovic@rt-rk.com>
	    Faraz Shahbazker  <fshahbazker@wavecomp.com>

sim/common/ChangeLog:
	* sim-bits.h (EXTEND9, EXTEND18 ,EXTEND19, EXTEND21,
	EXTEND26): New macros.

sim/mips/ChangeLog:
	* Makefile.in (IGEN_INCLUDE): Add mips3264r6.igen.
	* configure: Regenerate.
	* configure.ac: Support mipsisa32r6 and mipsisa64r6.
	(sim_engine_run): Pick simulator model from processor specified
	in e_flags.
	* cp1.c (value_fpr): Handle fmt_dc32.
	(fp_unary, fp_binary): Zero initialize locals.
	(update_fcsr, fp_classify, fp_rint, fp_r6_cmp, inner_fmac,
	fp_fmac, fp_min, fp_max, fp_mina, fp_maxa, fp_fmadd, fp_fmsub):
	New functions.
	(sim_fpu_class_mips_mapping): New.
	* cp1.h (fcsr_ABS2008_mask, fcsr_ABS2008_shift): New define.
	* interp.c (MIPSR6_P): New.
	(load_word): Allow unaligned memory access for MIPSR6.
	* micromips.igen (sc, scd): Adapt to new do_sc* helper signature.
	* mips.igen: Add *r6 models.
	(signal_if_cti, forbiddenslot32): New helpers.
	(delayslot32): Use signal_if_cti.
	(do_sc, do_scd); Add store_ll_bit parameter.
	(sc, scd): Adapt to previous change.
	(nal, beq, bal): New definitions for *r6.
	(sll): Split nop and ssnop cases into ...
	(nop, ssnop): New definitions.
	(loadstore_ea): Use the 32-bit compatibility adressing.
	(cache): Split logic into ...
	(do_cache): New helper.
	(check_fpu): Select IEEE 754-2008 mode for R6.
	(not_word_value, unpredictable, check_mt_hilo, check_mf_hilo,
	check_multi_hilo, check_div_hilo, check_u64, do_dmfc1b, add,
	li, addu, and, andi, bgez, bgtz, blez, bltz, bne, break, dadd,
	daddiu, daddu, dror, dror32, drorv, dsll, dsll32, dsllv, dsra,
	dsra32, dsrav, dsrl, dsrl32, dsub, dsubu, j, jal, jalr,
	jalr.hb, lb, lbu, ld, lh, lhu, lui, lw, lwu, nor, or, ori, ror,
	rorv, sb, sd, sh, sll, sllv, slt, slti, sltiu, sltu, sra, srav,
	srl, srlv, sub, subu, sw, sync, syscall, teq, tge, tgeu, tlt,
	tltu, tne, xor, xori, check_fmt_p, do_load_double,
	do_store_double, abs.FMT, add.FMT, ceil.l.FMT, ceil.w.FMT,
	cfc1, ctc1, cvt.d.FMT, cvt.l.FMT, cvt.w.FMT, div.FMT, dfmc1,
	dmtc1, floor.l.FMT, floor.w.FMT, ldc1, lwc1, mfc1, mov.FMT,
	mtc1, mul.FMT, recip.FMT, round.l.FMT, round.w.FMT, rsqrt.FMT,
	sdc1, sqrt.FMT, sub.FMT, swc1, trunc.l.FMT, trunc.w.FMT, bc0f,
	bc0fl, bc0t, bc0tl, dmfc0, dmtc0, eret, mfc0, mtc0, cop, tlbp,
	tlbr, tlbwi, tlbwr): Enable on *r6 models.
	* mips3264r2.igen (dext, dextm, dextu, di, dins, dinsm, dinsu,
	dsbh, dshd, ei, ext, mfhc1, mthc1, ins, seb, seh, synci, rdhwr,
	wsbh): Likewise.
	* mips3264r6.igen: New file.
	* sim-main.h (FP_formats): Add fmt_dc32.
	(FORBIDDEN_SLOT): New macros.
	(simFORBIDDENSLOT, FP_R6CMP_*, FP_R6CLASS_*): New defines.
	(fp_r6_cmp, fp_classify, fp_rint, fp_min, fp_max, fp_mina,
	fp_maxa, fp_fmadd, fp_fmsub): New declarations.
	(R6Compare, Classify, RoundToIntegralExact, Min, Max, MinA,
	MaxA, FusedMultiplyAdd, FusedMultiplySub): New macros. Wrapping
	previous declarations.

sim/testsuite/mips/ChangeLog:
	* basic.exp: Add r6-*.s tests.
	(run_r6_removed_test): New function.
	(run_endian_tests): New function.
	* hilo-hazard-3.s: Skip for mips*r6.
	* r2-fpu.s: New test.
	* r6-64.s: New test.
	* r6-branch.s: New test.
	* r6-forbidden.s: New test.
	* r6-fpu.s: New test.
	* r6-llsc-dp.s: New test.
	* r6-llsc-wp.s: New test.
	* r6-removed.csv: New test.
	* r6-removed.s: New test.
	* r6.s: New test.
	* utils-r6.inc: New inc.
2022-02-04 19:37:26 -05:00

170 lines
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# MIPS simulator instruction tests
sim_init
# Do "run_sim_test TESTFILE MODELS" for each combination of the
# mf{lo,hi} -> mult/div/mt{lo,hi} hazard described in mips.igen.
# Insert NOPS nops after the mflo or mfhi.
proc run_hilo_test {testfile models nops} {
foreach reg {lo hi} {
foreach insn "{mult\t\$4,\$4} {div\t\$0,\$4,\$4} {mt$reg\t\$4}" {
set contents ""
append contents "\t.macro hilo\n"
append contents "\tmf$reg\t\$4\n"
append contents "\t.rept\t$nops\n"
append contents "\tnop\n"
append contents "\t.endr\n"
append contents "\t$insn\n"
append contents "\t.endm"
verbose -log "HILO test:\n$contents"
set file [open hilo-hazard.inc w]
puts $file $contents
close $file
run_sim_test $testfile $models
}
}
}
# Runs micromips tests by adding -mmicromips to as options
proc run_micromips_test { name requested_machs } {
global ASFLAGS_FOR_TARGET
set ASFLAGS_FOR_TARGET "-mmicromips"
run_sim_test $name $requested_machs
unset ASFLAGS_FOR_TARGET
}
# Runs endian tests
proc run_endian_tests { name requested_machs } {
global ASFLAGS_FOR_TARGET
global LDFLAGS_FOR_TARGET
run_sim_test $name $requested_machs
set ASFLAGS_FOR_TARGET "-EL"
set LDFLAGS_FOR_TARGET "-EL"
run_sim_test $name $requested_machs
unset ASFLAGS_FOR_TARGET
unset LDFLAGS_FOR_TARGET
}
# Runs all specified tests
proc run_sim_tests { name requested_machs { requested_micromips_machs "" } } {
run_sim_test $name $requested_machs
run_micromips_test $name $requested_micromips_machs
}
# Runs the combination of instructions removed in R6 through the testsuite
proc run_r6_removed_test {testfile models} {
global subdir srcdir
set fd [open "$srcdir/$subdir/r6-removed.csv" r]
set file_data [read $fd]
close $fd
set data [split $file_data "\n"]
foreach line $data {
set line_contents [split $line ","]
set mnemonic [lindex $line_contents 0]
set insn [lindex $line_contents 1]
if {[string compare $insn ""] == 1} {
set contents ""
append contents ".macro removed_instr\n"
append contents ".word $insn\n"
append contents "nop\n"
append contents ".endm"
verbose -log "r6-removed test: $mnemonic\n$contents"
set file [open r6-removed.inc w]
puts $file $contents
close $file
run_sim_test $testfile $models
}
}
}
if {[istarget *]} {
# Used to locate the `run` program.
global arch
set arch "mips"
set dspmodels ""
set mdmxmodels ""
set micromipsmodels ""
set micromipsdspmodels ""
if {[istarget mipsisa64sb1*-*-elf]} {
set models "sb1"
set submodels "mips1 mips2 mips3 mips4 mips32 mips64"
append mdmxmodels " mips64"
} elseif {[istarget mipsisa64r6*-*-elf]} {
set models "mips32r6 mips64r6"
set submodels ""
} elseif {[istarget mipsisa64*-*-elf]} {
set models "mips32 mips64 mips32r2 mips64r2"
set submodels "mips1 mips2 mips3 mips4"
append dspmodels " mips32r2 mips64r2"
append mdmxmodels " mips64 mips32r2 mips64r2"
} elseif {[istarget mips*-sde-elf*] || [istarget mips*-mti-elf*]} {
set models "mips32 mips64 mips32r2 mips64r2 mips32r6 mips64r6"
set submodels ""
append dspmodels " mips32r2 mips64r2 mips32r6 mips64r6"
append mdmxmodels " mips64 mips32r2 mips64r2 mips32r6 mips64r6"
append micromipsmodels " mips32r2 mips64r2"
append micromipsdspmodels " mips32r2 mips64r2"
} elseif {[istarget mipsisa32r6*-*-elf]} {
set models "mips32r6"
set submodels ""
} elseif {[istarget mipsisa32*-*-elf]} {
set models "mips32 mips32r2"
set submodels "mips1 mips2"
append dspmodels " mips32r2"
append mdmxmodels " mips32r2"
append micromipsmodels " mips32r2"
append micromipsdspmodels " mips32r2"
} elseif {[istarget mips64vr*-*-elf]} {
set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500"
set submodels "mips1 mips2 mips3 mips4"
} elseif {[istarget mips64*-*-elf]} {
set models "mips3"
set submodels "mips1 mips2"
} else {
# fall back to just testing mips1 code.
set models "mips1"
set submodels ""
}
append submodels " " $models
set cpu_option -march
run_sim_tests sanity.s $submodels $micromipsmodels
foreach nops {0 1} {
run_hilo_test hilo-hazard-1.s $models $nops
run_hilo_test hilo-hazard-2.s $models $nops
}
run_hilo_test hilo-hazard-3.s $models 2
run_hilo_test hilo-hazard-4.s $micromipsmodels 2
run_sim_test fpu64-ps.s $submodels
run_sim_test fpu64-ps-sb1.s $submodels
run_sim_test mdmx-ob.s $mdmxmodels
run_sim_test mdmx-ob-sb1.s $mdmxmodels
run_sim_tests mips32-dsp.s $dspmodels $micromipsdspmodels
run_sim_tests mips32-dsp2.s $dspmodels $micromipsdspmodels
run_sim_test r2-fpu.s $models
run_sim_test r6-fpu.s $models
run_sim_test r6.s $models
run_sim_test r6-forbidden.s $models
run_r6_removed_test r6-removed.s $models
run_sim_test r6-64.s $models
run_sim_test r6-branch.s $models
run_endian_tests r6-llsc-wp.s $models
run_endian_tests r6-llsc-dp.s $models
}