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binutils-gdb/sim/testsuite
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Jaydeep Patil 3224e32fb8 sim: riscv: Add support for compressed integer instructions 
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.

Approved-By: Andrew Burgess <aburgess@redhat.com>
2024-02-13 11:04:04 +00:00
..
aarch64 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
arm sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
avr sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
bfin sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
bpf sim: bpf: remove support for ldinddw and ldabsdw instructions 2024-01-29 22:25:19 +01:00
common sim: Fix compile errors 2024-01-12 21:48:25 +02:00
config sim: testsuite: rework sim_init usage 2021-11-26 19:48:05 -05:00
cr16 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
cris Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00
d10v sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
example-synacor sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
frv sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
ft32 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
h8300 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
iq2000 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
lib sim prune_warnings 2023-08-19 12:41:32 +09:30
lm32 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
m32c Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00
m32r sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
m68hc11 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
mcore Yet another fix for mcore-sim (rotli) 2023-12-18 22:04:25 -07:00
microblaze sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
mips Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00
mn10300 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
moxie sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
msp430 sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
or1k Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00
pru Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00
riscv sim: riscv: Add support for compressed integer instructions 2024-02-13 11:04:04 +00:00
sh sim: testsuite: cleanup the istarget * logic 2022-02-16 00:36:47 -05:00
v850 Fix for v850e divq instruction 2022-04-06 11:10:40 -04:00
.gitignore sim: tests: ignore generated tests 2012-03-19 03:51:09 +00:00
ChangeLog-2021 sim: rename ChangeLog files to ChangeLog-2021 2021-08-17 20:27:36 -04:00
local.mk Update copyright year range in header of all files managed by GDB 2024-01-12 15:49:57 +00:00