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51 lines
2.0 KiB
Plaintext
51 lines
2.0 KiB
Plaintext
need to review ASTAT write behavior
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how to model RETE and IVG0 bit in IPEND ...
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model the loop buffer ? this means no ifetches because they're cached.
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see page 4-26 in Blackfin PRM under hardware loops.
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handle DSPID at 0xffe05000
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CEC should handle multiple exceptions at same address. would need
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exception processing to be delayed ? at least needs a stack for
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the CEC to pop things off.
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R0 = [SP++]; gets traced as R0 = [P6++];
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merge dv-bfin_evt with dv-bfin_cec since the EVT regs are part of the CEC
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fix single stepping over debug assert instructions in hardware
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exception in IVG5 causes double fault ?
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SIC int forwarding doesn't accurately reflect the hardware. what the sim
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does is:
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- device generates an interrupt
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- int is sent to SIC
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- SIC logs it into its ISR
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- so long as SIC's IMASK allows it, bits set in ISR generate
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an interrupt to the CEC
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- no way to clear the SIC's ISR
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the way the hardware works is that the device monitors the interrupt level and
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the SIC's ISR bits are basically hardwired from each peripheral. so when the
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device has its interrupt cleared, the bit in the SIC's ISR is automatically
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cleared as well.
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perhaps the only way to model this behavior in the sim is to have each device
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set up an event callback that sends out a port event: a level of 0 means the
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int has been ACKed and the SIC can clear its ISR while a level of 1 means the
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int is being generated still. if the device is still generating an interrupt,
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it can reschedule itself again.
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insns that cause an interrupt don't seem to be processed at the right time.
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for example, setup a glue device that generates an interrupt upon right.
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when the store insn is executed, the interrupt is taken right away instead
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of being scheduled *after* the insn has finished executing. difference is
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that RETI needs to point to the *next* insn and not the store insn.
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tests:
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- check AN bits with Dreg subtraction
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R0 = R1 - R2;
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- check astat bits with vector add/sub +|+
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- check acc with VIT_MAX and similiar insns
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