mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-30 21:44:19 +08:00
fa8b7c2128
This adds the OpenRISC 32-bit sim target. The OpenRISC sim is a CGEN based sim so the bulk of the code is generated from the .cpu files by CGEN. The engine decode and execute logic in mloop uses scache with pseudo-basic-block extraction and supports both full and fast (switch) modes. The sim does not implement an mmu at the moment. The sim does implement fpu instructions via the common sim-fpu implementation. sim/ChangeLog: 2017-12-12 Stafford Horne <shorne@gmail.com> Peter Gavin <pgavin@gmail.com> * configure.tgt: Add or1k sim. * or1k/README: New file. * or1k/Makefile.in: New file. * or1k/configure.ac: New file. * or1k/mloop.in: New file. * or1k/or1k-sim.h: New file. * or1k/or1k.c: New file. * or1k/sim-if.c: New file. * or1k/sim-main.h: New file. * or1k/traps.c: New file.
109 lines
2.0 KiB
Plaintext
109 lines
2.0 KiB
Plaintext
dnl Note that this file is intended to be included at the m4 level and not
|
|
dnl the shell level, so use sinclude(...) to pull it in.
|
|
|
|
# WHEN ADDING ENTRIES TO THIS MATRIX:
|
|
|
|
# Make sure that the left side always has two dashes. Otherwise you
|
|
# can get spurious matches. Even for unambiguous cases, do this as a
|
|
# convention, else the table becomes a real mess to understand and
|
|
# maintain.
|
|
|
|
dnl glue to avoid code duplication at top level
|
|
m4_ifndef([SIM_ARCH], [AC_DEFUN([SIM_ARCH],[sim_arch=$1])])
|
|
|
|
sim_igen=no
|
|
sim_arch=
|
|
case "${target}" in
|
|
aarch64*-*-*)
|
|
SIM_ARCH(aarch64)
|
|
;;
|
|
arm*-*-*)
|
|
SIM_ARCH(arm)
|
|
;;
|
|
avr*-*-*)
|
|
SIM_ARCH(avr)
|
|
;;
|
|
bfin-*-*)
|
|
SIM_ARCH(bfin)
|
|
;;
|
|
cr16*-*-*)
|
|
SIM_ARCH(cr16)
|
|
;;
|
|
cris-*-* | crisv32-*-*)
|
|
SIM_ARCH(cris)
|
|
;;
|
|
d10v-*-*)
|
|
SIM_ARCH(d10v)
|
|
;;
|
|
frv-*-*)
|
|
SIM_ARCH(frv)
|
|
;;
|
|
h8300*-*-*)
|
|
SIM_ARCH(h8300)
|
|
;;
|
|
iq2000-*-*)
|
|
SIM_ARCH(iq2000)
|
|
;;
|
|
lm32-*-*)
|
|
SIM_ARCH(lm32)
|
|
;;
|
|
m32c-*-*)
|
|
SIM_ARCH(m32c)
|
|
;;
|
|
m32r-*-*)
|
|
SIM_ARCH(m32r)
|
|
;;
|
|
m68hc11-*-*|m6811-*-*)
|
|
SIM_ARCH(m68hc11)
|
|
;;
|
|
mcore-*-*)
|
|
SIM_ARCH(mcore)
|
|
;;
|
|
microblaze-*-*)
|
|
SIM_ARCH(microblaze)
|
|
;;
|
|
mips*-*-*)
|
|
SIM_ARCH(mips)
|
|
sim_igen=yes
|
|
;;
|
|
mn10300*-*-*)
|
|
SIM_ARCH(mn10300)
|
|
sim_igen=yes
|
|
;;
|
|
moxie-*-*)
|
|
SIM_ARCH(moxie)
|
|
;;
|
|
msp430*-*-*)
|
|
SIM_ARCH(msp430)
|
|
;;
|
|
or1k-*-* | or1knd-*-*)
|
|
SIM_ARCH(or1k)
|
|
;;
|
|
rl78-*-*)
|
|
SIM_ARCH(rl78)
|
|
;;
|
|
rx-*-*)
|
|
SIM_ARCH(rx)
|
|
;;
|
|
sh64*-*-*)
|
|
SIM_ARCH(sh64)
|
|
;;
|
|
sh*-*-*)
|
|
SIM_ARCH(sh)
|
|
;;
|
|
sparc-*-rtems*|sparc-*-elf*)
|
|
SIM_ARCH(erc32)
|
|
;;
|
|
powerpc*-*-*)
|
|
SIM_ARCH(ppc)
|
|
;;
|
|
ft32-*-*)
|
|
SIM_ARCH(ft32)
|
|
;;
|
|
v850*-*-*)
|
|
SIM_ARCH(v850)
|
|
sim_igen=yes
|
|
;;
|
|
esac
|
|
AC_SUBST(sim_arch)
|