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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
349 lines
9.8 KiB
C
349 lines
9.8 KiB
C
/* mmix-opc.c -- MMIX opcode table
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Copyright (C) 2001-2024 Free Software Foundation, Inc.
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Written by Hans-Peter Nilsson (hp@bitrange.com)
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include <stdio.h>
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#include "opcode/mmix.h"
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#include "symcat.h"
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/* Register-name-table for special registers. */
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const struct mmix_spec_reg mmix_spec_regs[] =
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{
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/* Keep rJ at top; it's the most frequently used one. */
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{"rJ", 4},
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{"rA", 21},
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{"rB", 0},
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{"rC", 8},
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{"rD", 1},
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{"rE", 2},
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{"rF", 22},
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{"rG", 19},
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{"rH", 3},
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{"rI", 12},
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{"rK", 15},
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{"rL", 20},
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{"rM", 5},
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{"rN", 9},
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{"rO", 10},
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{"rP", 23},
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{"rQ", 16},
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{"rR", 6},
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{"rS", 11},
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{"rT", 13},
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{"rU", 17},
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{"rV", 18},
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{"rW", 24},
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{"rX", 25},
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{"rY", 26},
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{"rZ", 27},
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{"rBB", 7},
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{"rTT", 14},
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{"rWW", 28},
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{"rXX", 29},
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{"rYY", 30},
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{"rZZ", 31},
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{NULL, 0}
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};
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/* Opcode-table. In order to cut down on redundant contents, we use helper
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macros. */
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/* All bits in the opcode-byte are significant. Add "| ..." expressions
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to add zero-bits. */
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#undef O
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#define O(m) ((unsigned long) (m) << 24UL), ((~(unsigned long) (m) & 255) << 24)
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/* Bits 7..1 of the opcode are significant. */
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#undef Z
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#define Z(m) ((unsigned long) (m) << 24), ((~(unsigned long) (m) & 254) << 24)
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/* For easier overview of the table. */
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#define N mmix_type_normal
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#define B mmix_type_branch
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#define C mmix_type_condbranch
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#define MB mmix_type_memaccess_byte
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#define MW mmix_type_memaccess_wyde
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#define MT mmix_type_memaccess_tetra
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#define MO mmix_type_memaccess_octa
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#define M mmix_type_memaccess_block
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#define J mmix_type_jsr
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#define P mmix_type_pseudo
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#define OP(y) XCONCAT2 (mmix_operands_,y)
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/* Groups of instructions specified here must, if all are matching the
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same instruction, be consecutive, in order more-specific to
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less-specific match. */
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const struct mmix_opcode mmix_opcodes[] =
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{
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{"trap", O (0), OP (xyz_opt), J},
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{"fcmp", O (1), OP (regs), N},
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{"flot", Z (8), OP (roundregs_z), N},
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{"fun", O (2), OP (regs), N},
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{"feql", O (3), OP (regs), N},
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{"flotu", Z (10), OP (roundregs_z), N},
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{"fadd", O (4), OP (regs), N},
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{"fix", O (5), OP (roundregs), N},
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{"sflot", Z (12), OP (roundregs_z), N},
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{"fsub", O (6), OP (regs), N},
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{"fixu", O (7), OP (roundregs), N},
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{"sflotu", Z (14), OP (roundregs_z), N},
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{"fmul", O (16), OP (regs), N},
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{"fcmpe", O (17), OP (regs), N},
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{"mul", Z (24), OP (regs_z), N},
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{"fune", O (18), OP (regs), N},
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{"feqle", O (19), OP (regs), N},
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{"mulu", Z (26), OP (regs_z), N},
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{"fdiv", O (20), OP (regs), N},
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{"fsqrt", O (21), OP (roundregs), N},
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{"div", Z (28), OP (regs_z), N},
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{"frem", O (22), OP (regs), N},
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{"fint", O (23), OP (roundregs), N},
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{"divu", Z (30), OP (regs_z), N},
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{"add", Z (0x20), OP (regs_z), N},
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{"2addu", Z (0x28), OP (regs_z), N},
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{"addu", Z (0x22), OP (regs_z), N},
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/* Synonym for ADDU. Put after ADDU, since we don't prefer it for
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disassembly. It's supposed to be used for addresses, so we make it
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a memory block reference for purposes of assembly. */
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{"lda", Z (0x22), OP (regs_z_opt), M},
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{"4addu", Z (0x2a), OP (regs_z), N},
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{"sub", Z (0x24), OP (regs_z), N},
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{"8addu", Z (0x2c), OP (regs_z), N},
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{"subu", Z (0x26), OP (regs_z), N},
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{"16addu", Z (0x2e), OP (regs_z), N},
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{"cmp", Z (0x30), OP (regs_z), N},
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{"sl", Z (0x38), OP (regs_z), N},
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{"cmpu", Z (0x32), OP (regs_z), N},
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{"slu", Z (0x3a), OP (regs_z), N},
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{"neg", Z (0x34), OP (neg), N},
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{"sr", Z (0x3c), OP (regs_z), N},
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{"negu", Z (0x36), OP (neg), N},
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{"sru", Z (0x3e), OP (regs_z), N},
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{"bn", Z (0x40), OP (regaddr), C},
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{"bnn", Z (0x48), OP (regaddr), C},
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{"bz", Z (0x42), OP (regaddr), C},
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{"bnz", Z (0x4a), OP (regaddr), C},
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{"bp", Z (0x44), OP (regaddr), C},
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{"bnp", Z (0x4c), OP (regaddr), C},
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{"bod", Z (0x46), OP (regaddr), C},
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{"bev", Z (0x4e), OP (regaddr), C},
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{"pbn", Z (0x50), OP (regaddr), C},
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{"pbnn", Z (0x58), OP (regaddr), C},
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{"pbz", Z (0x52), OP (regaddr), C},
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{"pbnz", Z (0x5a), OP (regaddr), C},
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{"pbp", Z (0x54), OP (regaddr), C},
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{"pbnp", Z (0x5c), OP (regaddr), C},
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{"pbod", Z (0x56), OP (regaddr), C},
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{"pbev", Z (0x5e), OP (regaddr), C},
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{"csn", Z (0x60), OP (regs_z), N},
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{"csnn", Z (0x68), OP (regs_z), N},
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{"csz", Z (0x62), OP (regs_z), N},
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{"csnz", Z (0x6a), OP (regs_z), N},
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{"csp", Z (0x64), OP (regs_z), N},
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{"csnp", Z (0x6c), OP (regs_z), N},
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{"csod", Z (0x66), OP (regs_z), N},
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{"csev", Z (0x6e), OP (regs_z), N},
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{"zsn", Z (0x70), OP (regs_z), N},
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{"zsnn", Z (0x78), OP (regs_z), N},
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{"zsz", Z (0x72), OP (regs_z), N},
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{"zsnz", Z (0x7a), OP (regs_z), N},
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{"zsp", Z (0x74), OP (regs_z), N},
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{"zsnp", Z (0x7c), OP (regs_z), N},
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{"zsod", Z (0x76), OP (regs_z), N},
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{"zsev", Z (0x7e), OP (regs_z), N},
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{"ldb", Z (0x80), OP (regs_z_opt), MB},
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{"ldt", Z (0x88), OP (regs_z_opt), MT},
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{"ldbu", Z (0x82), OP (regs_z_opt), MB},
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{"ldtu", Z (0x8a), OP (regs_z_opt), MT},
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{"ldw", Z (0x84), OP (regs_z_opt), MW},
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{"ldo", Z (0x8c), OP (regs_z_opt), MO},
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{"ldwu", Z (0x86), OP (regs_z_opt), MW},
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{"ldou", Z (0x8e), OP (regs_z_opt), MO},
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{"ldsf", Z (0x90), OP (regs_z_opt), MT},
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/* This doesn't seem to access memory, just the TLB. */
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{"ldvts", Z (0x98), OP (regs_z_opt), M},
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{"ldht", Z (0x92), OP (regs_z_opt), MT},
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/* Neither does this per-se. */
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{"preld", Z (0x9a), OP (x_regs_z), N},
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{"cswap", Z (0x94), OP (regs_z_opt), MO},
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{"prego", Z (0x9c), OP (x_regs_z), N},
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{"ldunc", Z (0x96), OP (regs_z_opt), MO},
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{"go", Z (GO_INSN_BYTE),
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OP (regs_z_opt), B},
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{"stb", Z (0xa0), OP (regs_z_opt), MB},
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{"stt", Z (0xa8), OP (regs_z_opt), MT},
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{"stbu", Z (0xa2), OP (regs_z_opt), MB},
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{"sttu", Z (0xaa), OP (regs_z_opt), MT},
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{"stw", Z (0xa4), OP (regs_z_opt), MW},
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{"sto", Z (0xac), OP (regs_z_opt), MO},
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{"stwu", Z (0xa6), OP (regs_z_opt), MW},
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{"stou", Z (0xae), OP (regs_z_opt), MO},
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{"stsf", Z (0xb0), OP (regs_z_opt), MT},
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{"syncd", Z (0xb8), OP (x_regs_z), M},
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{"stht", Z (0xb2), OP (regs_z_opt), MT},
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{"prest", Z (0xba), OP (x_regs_z), M},
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{"stco", Z (0xb4), OP (x_regs_z), MO},
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{"syncid", Z (0xbc), OP (x_regs_z), M},
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{"stunc", Z (0xb6), OP (regs_z_opt), MO},
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{"pushgo", Z (PUSHGO_INSN_BYTE),
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OP (pushgo), J},
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/* Synonym for OR with a zero Z. */
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{"set", O (0xc1)
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| 0xff, OP (set), N},
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{"or", Z (0xc0), OP (regs_z), N},
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{"and", Z (0xc8), OP (regs_z), N},
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{"orn", Z (0xc2), OP (regs_z), N},
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{"andn", Z (0xca), OP (regs_z), N},
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{"nor", Z (0xc4), OP (regs_z), N},
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{"nand", Z (0xcc), OP (regs_z), N},
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{"xor", Z (0xc6), OP (regs_z), N},
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{"nxor", Z (0xce), OP (regs_z), N},
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{"bdif", Z (0xd0), OP (regs_z), N},
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{"mux", Z (0xd8), OP (regs_z), N},
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{"wdif", Z (0xd2), OP (regs_z), N},
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{"sadd", Z (0xda), OP (regs_z), N},
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{"tdif", Z (0xd4), OP (regs_z), N},
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{"mor", Z (0xdc), OP (regs_z), N},
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{"odif", Z (0xd6), OP (regs_z), N},
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{"mxor", Z (0xde), OP (regs_z), N},
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{"seth", O (0xe0), OP (reg_yz), N},
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{"setmh", O (0xe1), OP (reg_yz), N},
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{"orh", O (0xe8), OP (reg_yz), N},
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{"ormh", O (0xe9), OP (reg_yz), N},
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{"setml", O (0xe2), OP (reg_yz), N},
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{"setl", O (SETL_INSN_BYTE),
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OP (reg_yz), N},
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{"orml", O (0xea), OP (reg_yz), N},
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{"orl", O (0xeb), OP (reg_yz), N},
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{"inch", O (INCH_INSN_BYTE),
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OP (reg_yz), N},
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{"incmh", O (INCMH_INSN_BYTE),
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OP (reg_yz), N},
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{"andnh", O (0xec), OP (reg_yz), N},
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{"andnmh", O (0xed), OP (reg_yz), N},
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{"incml", O (INCML_INSN_BYTE),
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OP (reg_yz), N},
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{"incl", O (0xe7), OP (reg_yz), N},
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{"andnml", O (0xee), OP (reg_yz), N},
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{"andnl", O (0xef), OP (reg_yz), N},
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{"jmp", Z (0xf0), OP (jmp), B},
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{"pop", O (0xf8), OP (pop), B},
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{"resume", O (0xf9)
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| 0xffff00, OP (resume), B},
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{"pushj", Z (0xf2), OP (pushj), J},
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{"save", O (0xfa)
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| 0xffff, OP (save), M},
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{"unsave", O (0xfb)
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| 0xffff00, OP (unsave), M},
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{"geta", Z (0xf4), OP (regaddr), N},
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{"sync", O (0xfc), OP (sync), N},
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{"swym", O (SWYM_INSN_BYTE),
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OP (xyz_opt), N},
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{"put", Z (0xf6) | 0xff00, OP (put), N},
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{"get", O (0xfe) | 0xffe0, OP (get), N},
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{"trip", O (0xff), OP (xyz_opt), J},
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/* We have mmixal pseudos in the ordinary instruction table so we can
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avoid the "set" vs. ".set" ambiguity that would be the effect if we
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had pseudos handled "normally" and defined NO_PSEUDO_DOT.
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Note that IS and GREG are handled fully by md_start_line_hook, so
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they're not here. */
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{"loc", ~0, ~0, OP (loc), P},
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{"prefix", ~0, ~0, OP (prefix), P},
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{"byte", ~0, ~0, OP (byte), P},
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{"wyde", ~0, ~0, OP (wyde), P},
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{"tetra", ~0, ~0, OP (tetra), P},
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{"octa", ~0, ~0, OP (octa), P},
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{"local", ~0, ~0, OP (local), P},
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{"bspec", ~0, ~0, OP (bspec), P},
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{"espec", ~0, ~0, OP (espec), P},
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{NULL, ~0, ~0, OP (none), N}
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};
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