mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2024-11-23 18:14:13 +08:00
1d506c26d9
This commit is the result of the following actions:
- Running gdb/copyright.py to update all of the copyright headers to
include 2024,
- Manually updating a few files the copyright.py script told me to
update, these files had copyright headers embedded within the
file,
- Regenerating gdbsupport/Makefile.in to refresh it's copyright
date,
- Using grep to find other files that still mentioned 2023. If
these files were updated last year from 2022 to 2023 then I've
updated them this year to 2024.
I'm sure I've probably missed some dates. Feel free to fix them up as
you spot them.
117 lines
3.7 KiB
C
117 lines
3.7 KiB
C
/* frv simulator support code
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Copyright (C) 1998-2024 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of the GNU simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef FRV_SIM_MAIN_H
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#define FRV_SIM_MAIN_H
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/* Main header for the frv. */
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/* This is a global setting. Different cpu families can't mix-n-match -scache
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and -pbb. However some cpu families may use -simple while others use
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one of -scache/-pbb. ???? */
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#define WITH_SCACHE_PBB 0
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#include "sim-basics.h"
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#include "opcodes/frv-desc.h"
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#include <stdbool.h>
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#include "opcodes/frv-opc.h"
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#include "arch.h"
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#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
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frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
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#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA)
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#include "sim-base.h"
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#include "cgen-sim.h"
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#include "frv-sim.h"
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#include "cache.h"
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#include "registers.h"
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#include "profile.h"
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void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
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extern void frv_sim_close (SIM_DESC sd, int quitting);
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#define SIM_CLOSE_HOOK(...) frv_sim_close (__VA_ARGS__)
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struct frv_sim_cpu {
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/* CPU specific parts go here.
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Note that in files that don't need to access these pieces WANT_CPU_FOO
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won't be defined and thus these parts won't appear. This is ok in the
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sense that things work. It is a source of bugs though.
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One has to of course be careful to not take the size of this
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struct and no structure members accessed in non-cpu specific files can
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go after here. Oh for a better language. */
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#if defined (WANT_CPU_FRVBF)
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FRVBF_CPU_DATA cpu_data;
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/* Control information for registers */
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FRV_REGISTER_CONTROL register_control;
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#define CPU_REGISTER_CONTROL(cpu) (& FRV_SIM_CPU (cpu)->register_control)
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FRV_VLIW vliw;
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#define CPU_VLIW(cpu) (& FRV_SIM_CPU (cpu)->vliw)
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FRV_CACHE insn_cache;
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#define CPU_INSN_CACHE(cpu) (& FRV_SIM_CPU (cpu)->insn_cache)
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FRV_CACHE data_cache;
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#define CPU_DATA_CACHE(cpu) (& FRV_SIM_CPU (cpu)->data_cache)
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FRV_PROFILE_STATE profile_state;
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#define CPU_PROFILE_STATE(cpu) (& FRV_SIM_CPU (cpu)->profile_state)
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int debug_state;
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#define CPU_DEBUG_STATE(cpu) (FRV_SIM_CPU (cpu)->debug_state)
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SI load_address;
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#define CPU_LOAD_ADDRESS(cpu) (FRV_SIM_CPU (cpu)->load_address)
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SI load_length;
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#define CPU_LOAD_LENGTH(cpu) (FRV_SIM_CPU (cpu)->load_length)
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SI load_flag;
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#define CPU_LOAD_SIGNED(cpu) (FRV_SIM_CPU (cpu)->load_flag)
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#define CPU_LOAD_LOCK(cpu) (FRV_SIM_CPU (cpu)->load_flag)
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SI store_flag;
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#define CPU_RSTR_INVALIDATE(cpu) (FRV_SIM_CPU (cpu)->store_flag)
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unsigned long elf_flags;
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#define CPU_ELF_FLAGS(cpu) (FRV_SIM_CPU (cpu)->elf_flags)
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#endif /* defined (WANT_CPU_FRVBF) */
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};
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#define FRV_SIM_CPU(cpu) ((struct frv_sim_cpu *) CPU_ARCH_DATA (cpu))
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/* Misc. */
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/* Catch address exceptions. */
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extern SIM_CORE_SIGNAL_FN frv_core_signal ATTRIBUTE_NORETURN;
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#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
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frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
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(TRANSFER), (ERROR))
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/* Default memory size. */
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#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */
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void frvbf_model_branch (SIM_CPU *, PCADDR, int hint);
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void frvbf_perform_writeback (SIM_CPU *);
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#endif
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