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380 lines
10 KiB
C
380 lines
10 KiB
C
/* Target-dependent code for QNX Neutrino x86.
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Copyright (C) 2003-2023 Free Software Foundation, Inc.
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Contributed by QNX Software Systems Ltd.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include "defs.h"
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#include "frame.h"
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#include "osabi.h"
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#include "regcache.h"
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#include "target.h"
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#include "i386-tdep.h"
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#include "i387-tdep.h"
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#include "nto-tdep.h"
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#include "solib.h"
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#include "solib-svr4.h"
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#ifndef X86_CPU_FXSR
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#define X86_CPU_FXSR (1L << 12)
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#endif
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/* Why 13? Look in our /usr/include/x86/context.h header at the
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x86_cpu_registers structure and you'll see an 'exx' junk register
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that is just filler. Don't ask me, ask the kernel guys. */
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#define NUM_GPREGS 13
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/* Mapping between the general-purpose registers in `struct xxx'
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format and GDB's register cache layout. */
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/* From <x86/context.h>. */
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static int i386nto_gregset_reg_offset[] =
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{
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7 * 4, /* %eax */
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6 * 4, /* %ecx */
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5 * 4, /* %edx */
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4 * 4, /* %ebx */
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11 * 4, /* %esp */
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2 * 4, /* %epb */
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1 * 4, /* %esi */
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0 * 4, /* %edi */
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8 * 4, /* %eip */
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10 * 4, /* %eflags */
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9 * 4, /* %cs */
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12 * 4, /* %ss */
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-1 /* filler */
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};
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/* Given a GDB register number REGNUM, return the offset into
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Neutrino's register structure or -1 if the register is unknown. */
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static int
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nto_reg_offset (int regnum)
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{
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if (regnum >= 0 && regnum < ARRAY_SIZE (i386nto_gregset_reg_offset))
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return i386nto_gregset_reg_offset[regnum];
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return -1;
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}
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static void
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i386nto_supply_gregset (struct regcache *regcache, char *gpregs)
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{
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struct gdbarch *gdbarch = regcache->arch ();
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i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
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gdb_assert (tdep->gregset_reg_offset == i386nto_gregset_reg_offset);
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i386_gregset.supply_regset (&i386_gregset, regcache, -1,
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gpregs, NUM_GPREGS * 4);
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}
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static void
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i386nto_supply_fpregset (struct regcache *regcache, char *fpregs)
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{
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if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR)
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i387_supply_fxsave (regcache, -1, fpregs);
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else
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i387_supply_fsave (regcache, -1, fpregs);
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}
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static void
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i386nto_supply_regset (struct regcache *regcache, int regset, char *data)
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{
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switch (regset)
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{
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case NTO_REG_GENERAL:
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i386nto_supply_gregset (regcache, data);
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break;
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case NTO_REG_FLOAT:
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i386nto_supply_fpregset (regcache, data);
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break;
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}
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}
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static int
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i386nto_regset_id (int regno)
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{
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if (regno == -1)
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return NTO_REG_END;
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else if (regno < I386_NUM_GREGS)
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return NTO_REG_GENERAL;
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else if (regno < I386_NUM_GREGS + I387_NUM_REGS)
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return NTO_REG_FLOAT;
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else if (regno < I386_SSE_NUM_REGS)
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return NTO_REG_FLOAT; /* We store xmm registers in fxsave_area. */
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return -1; /* Error. */
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}
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static int
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i386nto_register_area (struct gdbarch *gdbarch,
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int regno, int regset, unsigned *off)
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{
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i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
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*off = 0;
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if (regset == NTO_REG_GENERAL)
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{
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if (regno == -1)
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return NUM_GPREGS * 4;
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*off = nto_reg_offset (regno);
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if (*off == -1)
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return 0;
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return 4;
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}
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else if (regset == NTO_REG_FLOAT)
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{
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unsigned off_adjust, regsize, regset_size, regno_base;
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/* The following are flags indicating number in our fxsave_area. */
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int first_four = (regno >= I387_FCTRL_REGNUM (tdep)
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&& regno <= I387_FISEG_REGNUM (tdep));
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int second_four = (regno > I387_FISEG_REGNUM (tdep)
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&& regno <= I387_FOP_REGNUM (tdep));
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int st_reg = (regno >= I387_ST0_REGNUM (tdep)
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&& regno < I387_ST0_REGNUM (tdep) + 8);
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int xmm_reg = (regno >= I387_XMM0_REGNUM (tdep)
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&& regno < I387_MXCSR_REGNUM (tdep));
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if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR)
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{
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off_adjust = 32;
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regsize = 16;
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regset_size = 512;
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/* fxsave_area structure. */
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if (first_four)
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{
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/* fpu_control_word, fpu_status_word, fpu_tag_word, fpu_operand
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registers. */
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regsize = 2; /* Two bytes each. */
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off_adjust = 0;
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regno_base = I387_FCTRL_REGNUM (tdep);
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}
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else if (second_four)
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{
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/* fpu_ip, fpu_cs, fpu_op, fpu_ds registers. */
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regsize = 4;
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off_adjust = 8;
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regno_base = I387_FISEG_REGNUM (tdep) + 1;
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}
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else if (st_reg)
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{
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/* ST registers. */
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regsize = 16;
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off_adjust = 32;
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regno_base = I387_ST0_REGNUM (tdep);
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}
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else if (xmm_reg)
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{
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/* XMM registers. */
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regsize = 16;
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off_adjust = 160;
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regno_base = I387_XMM0_REGNUM (tdep);
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}
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else if (regno == I387_MXCSR_REGNUM (tdep))
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{
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regsize = 4;
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off_adjust = 24;
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regno_base = I387_MXCSR_REGNUM (tdep);
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}
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else
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{
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/* Whole regset. */
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gdb_assert (regno == -1);
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off_adjust = 0;
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regno_base = 0;
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regsize = regset_size;
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}
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}
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else
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{
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regset_size = 108;
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/* fsave_area structure. */
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if (first_four || second_four)
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{
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/* fpu_control_word, ... , fpu_ds registers. */
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regsize = 4;
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off_adjust = 0;
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regno_base = I387_FCTRL_REGNUM (tdep);
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}
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else if (st_reg)
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{
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/* One of ST registers. */
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regsize = 10;
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off_adjust = 7 * 4;
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regno_base = I387_ST0_REGNUM (tdep);
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}
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else
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{
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/* Whole regset. */
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gdb_assert (regno == -1);
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off_adjust = 0;
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regno_base = 0;
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regsize = regset_size;
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}
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}
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if (regno != -1)
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*off = off_adjust + (regno - regno_base) * regsize;
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else
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*off = 0;
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return regsize;
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}
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return -1;
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}
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static int
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i386nto_regset_fill (const struct regcache *regcache, int regset, char *data)
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{
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if (regset == NTO_REG_GENERAL)
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{
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int regno;
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for (regno = 0; regno < NUM_GPREGS; regno++)
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{
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int offset = nto_reg_offset (regno);
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if (offset != -1)
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regcache->raw_collect (regno, data + offset);
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}
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}
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else if (regset == NTO_REG_FLOAT)
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{
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if (nto_cpuinfo_valid && nto_cpuinfo_flags | X86_CPU_FXSR)
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i387_collect_fxsave (regcache, -1, data);
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else
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i387_collect_fsave (regcache, -1, data);
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}
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else
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return -1;
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return 0;
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}
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/* Return whether THIS_FRAME corresponds to a QNX Neutrino sigtramp
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routine. */
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static int
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i386nto_sigtramp_p (frame_info_ptr this_frame)
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{
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CORE_ADDR pc = get_frame_pc (this_frame);
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const char *name;
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find_pc_partial_function (pc, &name, NULL, NULL);
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return name && strcmp ("__signalstub", name) == 0;
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}
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/* Assuming THIS_FRAME is a QNX Neutrino sigtramp routine, return the
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address of the associated sigcontext structure. */
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static CORE_ADDR
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i386nto_sigcontext_addr (frame_info_ptr this_frame)
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{
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struct gdbarch *gdbarch = get_frame_arch (this_frame);
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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gdb_byte buf[4];
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CORE_ADDR ptrctx;
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/* We store __ucontext_t addr in EDI register. */
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get_frame_register (this_frame, I386_EDI_REGNUM, buf);
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ptrctx = extract_unsigned_integer (buf, 4, byte_order);
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ptrctx += 24 /* Context pointer is at this offset. */;
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return ptrctx;
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}
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static void
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init_i386nto_ops (void)
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{
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nto_regset_id = i386nto_regset_id;
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nto_supply_gregset = i386nto_supply_gregset;
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nto_supply_fpregset = i386nto_supply_fpregset;
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nto_supply_altregset = nto_dummy_supply_regset;
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nto_supply_regset = i386nto_supply_regset;
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nto_register_area = i386nto_register_area;
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nto_regset_fill = i386nto_regset_fill;
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nto_fetch_link_map_offsets =
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svr4_ilp32_fetch_link_map_offsets;
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}
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static void
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i386nto_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
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{
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i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
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static struct target_so_ops nto_svr4_so_ops;
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/* Deal with our strange signals. */
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nto_initialize_signals ();
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/* NTO uses ELF. */
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i386_elf_init_abi (info, gdbarch);
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/* Neutrino rewinds to look more normal. Need to override the i386
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default which is [unfortunately] to decrement the PC. */
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set_gdbarch_decr_pc_after_break (gdbarch, 0);
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tdep->gregset_reg_offset = i386nto_gregset_reg_offset;
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tdep->gregset_num_regs = ARRAY_SIZE (i386nto_gregset_reg_offset);
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tdep->sizeof_gregset = NUM_GPREGS * 4;
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tdep->sigtramp_p = i386nto_sigtramp_p;
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tdep->sigcontext_addr = i386nto_sigcontext_addr;
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tdep->sc_reg_offset = i386nto_gregset_reg_offset;
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tdep->sc_num_regs = ARRAY_SIZE (i386nto_gregset_reg_offset);
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/* Setjmp()'s return PC saved in EDX (5). */
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tdep->jb_pc_offset = 20; /* 5x32 bit ints in. */
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set_solib_svr4_fetch_link_map_offsets
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(gdbarch, svr4_ilp32_fetch_link_map_offsets);
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/* Initialize this lazily, to avoid an initialization order
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dependency on solib-svr4.c's _initialize routine. */
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if (nto_svr4_so_ops.in_dynsym_resolve_code == NULL)
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{
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nto_svr4_so_ops = svr4_so_ops;
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/* Our loader handles solib relocations differently than svr4. */
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nto_svr4_so_ops.relocate_section_addresses
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= nto_relocate_section_addresses;
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/* Supply a nice function to find our solibs. */
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nto_svr4_so_ops.find_and_open_solib
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= nto_find_and_open_solib;
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/* Our linker code is in libc. */
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nto_svr4_so_ops.in_dynsym_resolve_code
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= nto_in_dynsym_resolve_code;
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}
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set_gdbarch_so_ops (gdbarch, &nto_svr4_so_ops);
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set_gdbarch_wchar_bit (gdbarch, 32);
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set_gdbarch_wchar_signed (gdbarch, 0);
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}
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void _initialize_i386nto_tdep ();
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void
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_initialize_i386nto_tdep ()
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{
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init_i386nto_ops ();
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gdbarch_register_osabi (bfd_arch_i386, 0, GDB_OSABI_QNXNTO,
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i386nto_init_abi);
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gdbarch_register_osabi_sniffer (bfd_arch_i386, bfd_target_elf_flavour,
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nto_elf_osabi_sniffer);
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}
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