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697 lines
18 KiB
C
697 lines
18 KiB
C
/* CPU family header for m32rbf.
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THIS FILE IS MACHINE GENERATED WITH CGEN.
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Copyright 1996-2022 Free Software Foundation, Inc.
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This file is part of the GNU simulators.
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This file is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef CPU_M32RBF_H
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#define CPU_M32RBF_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 2
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* The size of an "int" needed to hold an instruction word.
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This is usually 32 bits, but some architectures needs 64 bits. */
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typedef CGEN_INSN_INT CGEN_INSN_WORD;
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#include "cgen-engine.h"
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* general registers */
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SI h_gr[16];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* control registers */
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USI h_cr[16];
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#define GET_H_CR(index) m32rbf_h_cr_get_handler (current_cpu, index)
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#define SET_H_CR(index, x) \
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do { \
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m32rbf_h_cr_set_handler (current_cpu, (index), (x));\
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;} while (0)
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/* accumulator */
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DI h_accum;
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#define GET_H_ACCUM() m32rbf_h_accum_get_handler (current_cpu)
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#define SET_H_ACCUM(x) \
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do { \
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m32rbf_h_accum_set_handler (current_cpu, (x));\
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;} while (0)
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/* condition bit */
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BI h_cond;
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#define GET_H_COND() CPU (h_cond)
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#define SET_H_COND(x) (CPU (h_cond) = (x))
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/* psw part of psw */
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UQI h_psw;
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#define GET_H_PSW() m32rbf_h_psw_get_handler (current_cpu)
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#define SET_H_PSW(x) \
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do { \
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m32rbf_h_psw_set_handler (current_cpu, (x));\
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;} while (0)
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/* backup psw */
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UQI h_bpsw;
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#define GET_H_BPSW() CPU (h_bpsw)
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#define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
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/* backup bpsw */
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UQI h_bbpsw;
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#define GET_H_BBPSW() CPU (h_bbpsw)
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#define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
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/* lock */
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BI h_lock;
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#define GET_H_LOCK() CPU (h_lock)
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#define SET_H_LOCK(x) (CPU (h_lock) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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} M32RBF_CPU_DATA;
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/* Cover fns for register access. */
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USI m32rbf_h_pc_get (SIM_CPU *);
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void m32rbf_h_pc_set (SIM_CPU *, USI);
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SI m32rbf_h_gr_get (SIM_CPU *, UINT);
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void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
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USI m32rbf_h_cr_get (SIM_CPU *, UINT);
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void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
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DI m32rbf_h_accum_get (SIM_CPU *);
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void m32rbf_h_accum_set (SIM_CPU *, DI);
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BI m32rbf_h_cond_get (SIM_CPU *);
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void m32rbf_h_cond_set (SIM_CPU *, BI);
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UQI m32rbf_h_psw_get (SIM_CPU *);
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void m32rbf_h_psw_set (SIM_CPU *, UQI);
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UQI m32rbf_h_bpsw_get (SIM_CPU *);
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void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
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UQI m32rbf_h_bbpsw_get (SIM_CPU *);
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void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
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BI m32rbf_h_lock_get (SIM_CPU *);
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void m32rbf_h_lock_set (SIM_CPU *, BI);
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/* These must be hand-written. */
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extern CPUREG_FETCH_FN m32rbf_fetch_register;
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extern CPUREG_STORE_FN m32rbf_store_register;
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typedef struct {
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UINT h_gr;
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} MODEL_M32R_D_DATA;
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typedef struct {
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int empty;
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} MODEL_TEST_DATA;
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/* Instruction argument buffer. */
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union sem_fields {
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struct { /* no operands */
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int empty;
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} sfmt_empty;
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struct { /* */
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UINT f_uimm8;
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} sfmt_clrpsw;
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struct { /* */
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UINT f_uimm4;
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} sfmt_trap;
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struct { /* */
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IADDR i_disp24;
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unsigned char out_h_gr_SI_14;
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} sfmt_bl24;
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struct { /* */
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IADDR i_disp8;
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unsigned char out_h_gr_SI_14;
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} sfmt_bl8;
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struct { /* */
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SI* i_dr;
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UINT f_hi16;
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UINT f_r1;
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unsigned char out_dr;
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} sfmt_seth;
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struct { /* */
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ADDR i_uimm24;
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SI* i_dr;
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UINT f_r1;
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unsigned char out_dr;
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} sfmt_ld24;
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struct { /* */
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SI* i_sr;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_h_gr_SI_14;
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} sfmt_jl;
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struct { /* */
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SI* i_sr;
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INT f_simm16;
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UINT f_r2;
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UINT f_uimm3;
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unsigned char in_sr;
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} sfmt_bset;
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struct { /* */
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SI* i_dr;
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UINT f_r1;
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UINT f_uimm5;
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unsigned char in_dr;
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unsigned char out_dr;
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} sfmt_slli;
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struct { /* */
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SI* i_dr;
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INT f_simm8;
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UINT f_r1;
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unsigned char in_dr;
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unsigned char out_dr;
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} sfmt_addi;
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struct { /* */
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SI* i_src1;
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SI* i_src2;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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unsigned char out_src2;
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} sfmt_st_plus;
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struct { /* */
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SI* i_src1;
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SI* i_src2;
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INT f_simm16;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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} sfmt_st_d;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_dr;
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unsigned char out_sr;
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} sfmt_ld_plus;
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struct { /* */
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IADDR i_disp16;
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SI* i_src1;
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SI* i_src2;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_src1;
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unsigned char in_src2;
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} sfmt_beq;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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UINT f_uimm16;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_and3;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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INT f_simm16;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_add3;
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struct { /* */
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SI* i_dr;
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SI* i_sr;
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UINT f_r1;
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UINT f_r2;
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unsigned char in_dr;
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unsigned char in_sr;
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unsigned char out_dr;
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} sfmt_add;
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#if WITH_SCACHE_PBB
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/* Writeback handler. */
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struct {
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/* Pointer to argbuf entry for insn whose results need writing back. */
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const struct argbuf *abuf;
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} write;
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/* x-before handler */
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struct {
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/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
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int first_p;
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} before;
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/* x-after handler */
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struct {
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int empty;
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} after;
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/* This entry is used to terminate each pbb. */
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struct {
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/* Number of insns in pbb. */
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int insn_count;
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/* Next pbb to execute. */
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SCACHE *next;
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SCACHE *branch_target;
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} chain;
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#endif
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};
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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IADDR addr;
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const IDESC *idesc;
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char trace_p;
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char profile_p;
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/* ??? Temporary hack for skip insns. */
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char skip_count;
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char unused;
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/* cpu specific data follows */
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union sem semantic;
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int written;
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union sem_fields fields;
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};
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/* A cached insn.
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??? SCACHE used to contain more than just argbuf. We could delete the
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type entirely and always just use ARGBUF, but for future concerns and as
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a level of abstraction it is left in. */
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struct scache {
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_IFMT_EMPTY_VARS \
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unsigned int length;
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#define EXTRACT_IFMT_EMPTY_CODE \
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length = 0; \
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#define EXTRACT_IFMT_ADD_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_ADD3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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INT f_simm16; \
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unsigned int length;
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#define EXTRACT_IFMT_ADD3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_AND3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_IFMT_AND3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_OR3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_IFMT_OR3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_ADDI_VARS \
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UINT f_op1; \
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UINT f_r1; \
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INT f_simm8; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDI_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8); \
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#define EXTRACT_IFMT_ADDV3_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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INT f_simm16; \
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unsigned int length;
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#define EXTRACT_IFMT_ADDV3_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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#define EXTRACT_IFMT_BC8_VARS \
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UINT f_op1; \
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UINT f_r1; \
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SI f_disp8; \
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unsigned int length;
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#define EXTRACT_IFMT_BC8_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
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#define EXTRACT_IFMT_BC24_VARS \
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UINT f_op1; \
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UINT f_r1; \
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SI f_disp24; \
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unsigned int length;
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#define EXTRACT_IFMT_BC24_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) << (2))) + (pc)); \
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#define EXTRACT_IFMT_BEQ_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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SI f_disp16; \
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unsigned int length;
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#define EXTRACT_IFMT_BEQ_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
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#define EXTRACT_IFMT_BEQZ_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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SI f_disp16; \
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unsigned int length;
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#define EXTRACT_IFMT_BEQZ_CODE \
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length = 4; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) << (2))) + (pc)); \
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#define EXTRACT_IFMT_CMP_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_IFMT_CMP_CODE \
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length = 2; \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_CMPI_VARS \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CMPI_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
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|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
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|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
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|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
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|
|
|
#define EXTRACT_IFMT_DIV_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_DIV_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_JL_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_JL_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_LD24_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_uimm24; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LD24_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24); \
|
|
|
|
#define EXTRACT_IFMT_LDI16_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_LDI16_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_MVFACHI_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVFACHI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_MVFC_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVFC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_MVTACHI_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVTACHI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_MVTC_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_MVTC_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_NOP_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_NOP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_SETH_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
UINT f_hi16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SETH_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_SLLI_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_shift_op2; \
|
|
UINT f_uimm5; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_SLLI_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_shift_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 3); \
|
|
f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5); \
|
|
|
|
#define EXTRACT_IFMT_ST_D_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_ST_D_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_TRAP_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_op2; \
|
|
UINT f_uimm4; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_TRAP_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
#define EXTRACT_IFMT_CLRPSW_VARS \
|
|
UINT f_op1; \
|
|
UINT f_r1; \
|
|
UINT f_uimm8; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_CLRPSW_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
|
f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
|
|
|
#define EXTRACT_IFMT_BSET_VARS \
|
|
UINT f_op1; \
|
|
UINT f_bit4; \
|
|
UINT f_uimm3; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
INT f_simm16; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BSET_CODE \
|
|
length = 4; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 32, 0, 4); \
|
|
f_bit4 = EXTRACT_MSB0_UINT (insn, 32, 4, 1); \
|
|
f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 32, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4); \
|
|
f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16); \
|
|
|
|
#define EXTRACT_IFMT_BTST_VARS \
|
|
UINT f_op1; \
|
|
UINT f_bit4; \
|
|
UINT f_uimm3; \
|
|
UINT f_op2; \
|
|
UINT f_r2; \
|
|
unsigned int length;
|
|
#define EXTRACT_IFMT_BTST_CODE \
|
|
length = 2; \
|
|
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
|
f_bit4 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
|
|
f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3); \
|
|
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
|
f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
|
|
|
/* Collection of various things for the trace handler to use. */
|
|
|
|
typedef struct trace_record {
|
|
IADDR pc;
|
|
/* FIXME:wip */
|
|
} TRACE_RECORD;
|
|
|
|
#endif /* CPU_M32RBF_H */
|