mirror of
https://sourceware.org/git/binutils-gdb.git
synced 2025-01-26 09:54:17 +08:00
3fa454e95f
* Followup patch for SCEI PR 15853 * First check-in of TX3904 interrupt controller devices for ECC. [sanitized] * First implementation of MIPS hardware interrupt emulation. Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware modules. Recognize TX39 target with "mips*tx39" pattern. * configure: Rebuilt. * sim-main.h (*): Added many macros defining bits in TX39 control registers. (SignalInterrupt): Send actual PC instead of NULL. (SignalNMIReset): New exception type. * interp.c (board): New variable for future use to identify a particular board being simulated. (mips_option_handler,mips_options): Added "--board" option. (interrupt_event): Send actual PC. (sim_open): Make memory layout conditional on board setting. (signal_exception): Initial implementation of hardware interrupt handling. Accept another break instruction variant for simulator exit. (decode_coproc): Implement RFE instruction for TX39. (mips.igen): Decode RFE instruction as such. start-sanitize-tx3904 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. * interp.c: Define "jmr3904" and "jmr3904debug" board types and bbegin to implement memory map. * dv-tx3904cpu.c: New file. * dv-tx3904irc.c: New file. end-sanitize-tx3904 |
||
---|---|---|
bfd | ||
binutils | ||
config | ||
gas | ||
gdb | ||
gprof | ||
include | ||
intl | ||
ld | ||
mmalloc | ||
opcodes | ||
readline | ||
sim | ||
.Sanitize | ||
Build-A-Release.mk | ||
ChangeLog | ||
config-ml.in | ||
config.guess | ||
config.sub | ||
configure | ||
configure.bat | ||
configure.in | ||
DOC.Sanitize | ||
install-sh | ||
install-texi.in | ||
Install.in | ||
intro.texi | ||
ltconfig | ||
ltmain.sh | ||
makeall.bat | ||
Makefile.in | ||
makefile.vms | ||
mpw-build.in | ||
mpw-config.in | ||
mpw-configure | ||
mpw-README | ||
Pack-A-Progressive | ||
setup.com | ||
tape-labels-tex.in | ||
test-build.mk |