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fd67aa1129
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
125 lines
5.7 KiB
C
125 lines
5.7 KiB
C
/* ARC instruction defintions.
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Copyright (C) 2016-2024 Free Software Foundation, Inc.
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Contributed by Claudiu Zissulescu (claziss@synopsys.com)
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This file is part of libopcodes.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software Foundation,
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Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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/* Common combinations of FLAGS. */
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#define FLAGS_NONE { 0 }
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#define FLAGS_F { C_F }
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#define FLAGS_CC { C_CC }
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#define FLAGS_CCF { C_CC, C_F }
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/* Common combination of arguments. */
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#define ARG_NONE { 0 }
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#define ARG_32BIT_RARBRC { RA, RB, RC }
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#define ARG_32BIT_ZARBRC { ZA, RB, RC }
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#define ARG_32BIT_RBRBRC { RB, RBdup, RC }
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#define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 }
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#define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 }
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#define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 }
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#define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 }
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#define ARG_32BIT_RALIMMRC { RA, LIMM, RC }
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#define ARG_32BIT_RARBLIMM { RA, RB, LIMM }
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#define ARG_32BIT_ZALIMMRC { ZA, LIMM, RC }
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#define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM }
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#define ARG_32BIT_RBRBLIMM { RB, RBdup, LIMM }
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#define ARG_32BIT_RALIMMU6 { RA, LIMM, UIMM6_20 }
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#define ARG_32BIT_ZALIMMU6 { ZA, LIMM, UIMM6_20 }
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#define ARG_32BIT_ZALIMMS12 { ZA, LIMM, SIMM12_20 }
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#define ARG_32BIT_RALIMMLIMM { RA, LIMM, LIMMdup }
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#define ARG_32BIT_ZALIMMLIMM { ZA, LIMM, LIMMdup }
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#define ARG_32BIT_RBRC { RB, RC }
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#define ARG_32BIT_ZARC { ZA, RC }
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#define ARG_32BIT_RBU6 { RB, UIMM6_20 }
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#define ARG_32BIT_ZAU6 { ZA, UIMM6_20 }
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#define ARG_32BIT_RBLIMM { RB, LIMM }
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#define ARG_32BIT_ZALIMM { ZA, LIMM }
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/* Macro to generate 2 operand extension instruction. */
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#define EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FL) \
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{ NAME, INSN2OP_BC (MOP,SOP), MINSN2OP_BC, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBRC, FL }, \
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{ NAME, INSN2OP_0C (MOP,SOP), MINSN2OP_0C, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZARC, FL }, \
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{ NAME, INSN2OP_BU (MOP,SOP), MINSN2OP_BU, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBU6, FL }, \
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{ NAME, INSN2OP_0U (MOP,SOP), MINSN2OP_0U, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZAU6, FL }, \
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{ NAME, INSN2OP_BL (MOP,SOP), MINSN2OP_BL, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBLIMM, FL }, \
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{ NAME, INSN2OP_0L (MOP,SOP), MINSN2OP_0L, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMM, FL },
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#define EXTINSN2OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
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EXTINSN2OPF(NAME, CPU, CLASS, SCLASS, MOP, SOP, FLAGS_F)
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/* Macro to generate 3 operand extesion instruction. */
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#define EXTINSN3OP(NAME, CPU, CLASS, SCLASS, MOP, SOP) \
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{ NAME, INSN3OP_ABC (MOP,SOP), MINSN3OP_ABC, CPU, CLASS, SCLASS, \
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ARG_32BIT_RARBRC, FLAGS_F }, \
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{ NAME, INSN3OP_0BC (MOP,SOP), MINSN3OP_0BC, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZARBRC, FLAGS_F }, \
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{ NAME, INSN3OP_CBBC (MOP,SOP), MINSN3OP_CBBC, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBRBRC, FLAGS_CCF }, \
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{ NAME, INSN3OP_ABU (MOP,SOP), MINSN3OP_ABU, CPU, CLASS, SCLASS, \
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ARG_32BIT_RARBU6, FLAGS_F }, \
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{ NAME, INSN3OP_0BU (MOP,SOP), MINSN3OP_0BU, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZARBU6, FLAGS_F }, \
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{ NAME, INSN3OP_CBBU (MOP,SOP), MINSN3OP_CBBU, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBRBU6, FLAGS_CCF }, \
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{ NAME, INSN3OP_BBS (MOP,SOP), MINSN3OP_BBS, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBRBS12, FLAGS_F }, \
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{ NAME, INSN3OP_ALC (MOP,SOP), MINSN3OP_ALC, CPU, CLASS, SCLASS, \
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ARG_32BIT_RALIMMRC, FLAGS_F }, \
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{ NAME, INSN3OP_ABL (MOP,SOP), MINSN3OP_ABL, CPU, CLASS, SCLASS, \
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ARG_32BIT_RARBLIMM, FLAGS_F }, \
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{ NAME, INSN3OP_0LC (MOP,SOP), MINSN3OP_0LC, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMRC, FLAGS_F }, \
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{ NAME, INSN3OP_0BL (MOP,SOP), MINSN3OP_0BL, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZARBLIMM, FLAGS_F }, \
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{ NAME, INSN3OP_C0LC (MOP,SOP), MINSN3OP_C0LC, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMRC, FLAGS_CCF }, \
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{ NAME, INSN3OP_CBBL (MOP,SOP), MINSN3OP_CBBL, CPU, CLASS, SCLASS, \
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ARG_32BIT_RBRBLIMM, FLAGS_CCF }, \
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{ NAME, INSN3OP_ALU (MOP,SOP), MINSN3OP_ALU, CPU, CLASS, SCLASS, \
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ARG_32BIT_RALIMMU6, FLAGS_F }, \
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{ NAME, INSN3OP_0LU (MOP,SOP), MINSN3OP_0LU, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMU6, FLAGS_F }, \
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{ NAME, INSN3OP_C0LU (MOP,SOP), MINSN3OP_C0LU, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMU6, FLAGS_CCF }, \
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{ NAME, INSN3OP_0LS (MOP,SOP), MINSN3OP_0LS, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMS12, FLAGS_F }, \
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{ NAME, INSN3OP_ALL (MOP,SOP), MINSN3OP_ALL, CPU, CLASS, SCLASS, \
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ARG_32BIT_RALIMMLIMM, FLAGS_F }, \
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{ NAME, INSN3OP_0LL (MOP,SOP), MINSN3OP_0LL, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMLIMM, FLAGS_F }, \
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{ NAME, INSN3OP_C0LL (MOP,SOP), MINSN3OP_C0LL, CPU, CLASS, SCLASS, \
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ARG_32BIT_ZALIMMLIMM, FLAGS_CCF },
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/* Extension instruction declarations. */
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EXTINSN2OP ("dsp_fp_flt2i", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
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EXTINSN2OP ("dsp_fp_i2flt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 44)
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EXTINSN2OP ("dsp_fp_sqrt", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 45)
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EXTINSN3OP ("dsp_fp_div", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE2, 7, 42)
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EXTINSN3OP ("dsp_fp_cmp", ARC_OPCODE_ARCv2EM, FLOAT, QUARKSE1, 7, 43)
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